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Participant
Participant
9,050 Views
Registered: ‎08-28-2009

KCU105 UART TX/RX incorrect pin assignments in provided XDC file, schematics (!), correct in UG917

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Suppose you want to use the USB_UART_TX on U1, the KU040. Which pin is it?

 

UG917 KCU105 User Guide: K26.

XTP392 KCU105 schematics: G25.

RDF0349 XDC file: G25.

Correct answer: (e.g. now working hardware): K26.

 

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Scholar
Scholar
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Registered: ‎06-05-2013

@jsgray We have added short note below the table to make it very clear that USB_UART_Sig nets are named from the perspective of the CP2105GM device.

 

So you just need to refer FPGA Pin and function. When you are looking for USB_UART_TX the pin is K26 not the G25.

 

I hope this is clear now. Please do check table and note

http://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf

 

-Pratham

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Hello @jsgray,

 

Please check this AR

http://www.xilinx.com/support/answers/64249.html

Regards,
Ashish
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Participant
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Registered: ‎08-28-2009

Thank you.

The referenced AR notes the information has been corrected in UG917.

However as I noted it has not been corrected in the official board schematics nor in the official XDC file.

I hope Xilinx makes these corrections so as to save other designers from also their wasting time tracking this down.

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Scholar
Scholar
16,933 Views
Registered: ‎06-05-2013

@jsgray We have added short note below the table to make it very clear that USB_UART_Sig nets are named from the perspective of the CP2105GM device.

 

So you just need to refer FPGA Pin and function. When you are looking for USB_UART_TX the pin is K26 not the G25.

 

I hope this is clear now. Please do check table and note

http://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf

 

-Pratham

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2012

Which version of UG917 are you refering? PLease note that Ver 1.4 is the latest.

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Participant
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Registered: ‎08-28-2009

Thank you for your prompt replies. Unfortunately you do not seem to grasp the problem.

 

The problem is: 2 out of 3 of the latest authoritative Xilinx documents on the KCU105 have mislabelled the TX and RX pins. Don't you think that is a serious problem that needs to be fixed by updates to XTP392 and RDF0349?

 

The latest UG917 KCU105 labels USB_UART_TX as K26.

The latest XTP392 KCU105 schematics labels USB_UART_TX as G25.

The latest RDF0349 XDC file labels USB_UART_TX as G25.

By trial and error I found the actual pin to transmit data from U1 is K26.

 

To make the problem quite plain, imagine you are a busy designer, bringing up your latest design iteration in hardware following correct functional simulation. You just need to wire out your UART TX signal. You consult the latest Xilinx provided XDC file from RDF0349, e.g. KCU_Rev1.0_07242015.xdc which contains:

 

# Bank  95 VCCO -          - IO_L2P_T0L_N2_FOE_B_65
set_property PACKAGE_PIN G25      [get_ports "USB_UART_TX"]
set_property IOSTANDARD  LVMOS18  [get_ports "USB_UART_TX"]

 

Because you are a careful engineer, you double check that with the UG917. Oh dear, they disagree. UG917 says USB_UART_TX is on K26.  No problem, let's consult the schematic. You open the latest XIlinx provided board schematics from the latest XTP392. It shows USB_UART_TX is definitely on G25! Huh. Do you believe the XDC file and the schematic, or the User's Guide? Right. You use the XDC file specification. You copy those lines into your design, build it, download it into the FPGA, nothing happens. Well, something happens -- your design is driving pin G25 high and low, which is also driven high by the USB UART transceiver. Not good!

 

Well, by this point, there is no getting past it. If you want to get this part of your design working you are going to have to disregard the pin assignments in Xilinx XDC file and Xilinx schematics (!) and rebuild your design with K26. You do that with some angst because if you are wrong there will be two drivers on the net and you don't want to damage the device.

 

You discover K26 is the right net. You are not amused.

 

You are left to wonder: why did Xilinx waste my time on this? When the aforementioned AR was done, why didn't Xilinx ALSO update the (usually authoritative, but now untrustworthy) schematics and XDC file with the correction as well? Now that this problem has been spelled out, is Xilinx going to revise XTP392 and RDF0349, or leave this pitfall for others to stumble into?

 

Thank you.

 

 

 

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Participant
Participant
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Registered: ‎08-28-2009

I reread the comment about "The USB_UART_sig nets are named from the perspective of the CP2105GM device." Thank you, that was helpful.

 

My world just did a 180 degree turn. I get it now. Table 1-17 on p. 52 in UG917 v1.4 is correct. The schematics and XDC file are correct. To transmit on the UART, simply drive USB_UART_RX on pin K26.

 

KCU_Rev1.0_07242015.xdc from RDF0349:

set_property PACKAGE_PIN K26      [get_ports "USB_UART_RX"]
set_property PACKAGE_PIN G25      [get_ports "USB_UART_TX"]

 

HOWEVER, the UG917 v1.4 Appendix D, Master Constraints File Listing, p.134, is incorrect and needs to be fixed.

set_property PACKAGE_PIN G25 [get_ports "USB_UART_RX"]
set_property PACKAGE_PIN K26 [get_ports "USB_UART_TX"]

 

Thank you.

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