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Participant gustavsvj
Participant
279 Views
Registered: ‎02-25-2019

KCU105 memory bandwidth

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Hi,

I'm planning on using the external memory on the KCU105 board. I've been reading the user guide and experimenting with the MIG. So far I've managed to write and read from the memory using JTAG.
My next step is to make a test of the memory bandwidth with something resembling the read and write patters I'm expecting. But what is the (very) theoretical maximum bandwidth of the KCU105?
I'm clocking the memory at 1200MHz so that gives a bandwidth of 2.4Gbps per pin. According to the datasheet the datapath is 64 bit wide so that would give a total memory bandwidth of 153.6Gbps.
Is this correct or am I missing something?

Kind regards,
Gustav

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Scholar drjohnsmith
Scholar
265 Views
Registered: ‎07-09-2009

Re: KCU105 memory bandwidth

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Theoretical max is what you have described,

But its a usless number...

Dont mean to offend , its also a very often asked questoin.

 

The DDR needs to fit in claibratoin / refresh cycles,

    The access ot the DDR will not be continous linear, so you have precharge and such considerations,

        The access is not single clock

The biggest constraint IMHO is , the way the code is written,

    Assuming you have a processor, then it will have limited bandwidth,

      will you have multiple DMA access's , if so then any one prcess will have statisticaly less access.

 

not least, there is no single definition of memory bandwidth..

 

https://www.sciencedirect.com/topics/computer-science/memory-bandwidth

https://en.wikipedia.org/wiki/Memory_bandwidth

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar drjohnsmith
Scholar
266 Views
Registered: ‎07-09-2009

Re: KCU105 memory bandwidth

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Theoretical max is what you have described,

But its a usless number...

Dont mean to offend , its also a very often asked questoin.

 

The DDR needs to fit in claibratoin / refresh cycles,

    The access ot the DDR will not be continous linear, so you have precharge and such considerations,

        The access is not single clock

The biggest constraint IMHO is , the way the code is written,

    Assuming you have a processor, then it will have limited bandwidth,

      will you have multiple DMA access's , if so then any one prcess will have statisticaly less access.

 

not least, there is no single definition of memory bandwidth..

 

https://www.sciencedirect.com/topics/computer-science/memory-bandwidth

https://en.wikipedia.org/wiki/Memory_bandwidth

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Participant gustavsvj
Participant
208 Views
Registered: ‎02-25-2019

Re: KCU105 memory bandwidth

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Dear John,

Thank you for your answer. No offence was taken.
It's my first time working with external memory and I was somewhat confused by the memory setup on the KCU105.

Kind regards,
Gustav

 

 

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Xilinx Employee
Xilinx Employee
146 Views
Registered: ‎03-04-2018

Re: KCU105 memory bandwidth

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Hi @gustavsvj ,

 

As drjohnsmith mentioned, basically the bandwidth depend on how to access the DDR memory.  In our example design with UltraScale/UltraScale+ FPGAs, you can do a bus utilization via example simulation.  PG150 describes it in page 257.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

1: Firstly, please check the bus utilization with example simulation.

2:Secondly, please check your utilization based on your access.

3:Finally, if the bus utilization is not as expected, please change your addressing.  Because MIG IP considers the group FSM based on the addressing, please see from 193 to 205 in the PG150.

 

Best regards,

kshimizu 

Product Application Engineer Xilinx Technical Support

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