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Visitor jeremyb
Visitor
2,383 Views
Registered: ‎09-18-2011

LCD Busy flag on Spartan 3E-1600

I’m trying to use the BUSY flag on the 16x2 LCD on the Spartan 3E-1600 development board from Digilent with no success.

 

I have LCD_DB setup to go tri-state when LCD_RW is high. According to the ST7066U datasheet when LCD_RS =0 and LCD_RW=1 then LCD_DB[7] contains the BUSY flag, and LCD_DB[6:0] contains the current address.  However after the bus settles it returns 0xFF in all instances.

 

I thought it was my code until I used a logic analyzer and saw it doing the same thing with the test program that ships with the board. After sending 0x01 (Clear Display) it requests the busy flag but ignores it (returns 0xFF)  and continues sending commands after a pre-set delay.

 

Are there any pull-up resisters or something preventing reads from the LCD display? Or am I screwing something up?

 

assign LCD_DB = (rw_reg == BUS_WRITE) ? db_reg : 8'bZ;	// 0: Write data to Display - 1: Read data from Display

 

The development board datasheet says  "When the StrataFlash memory is disabled (SF_CE0 = High), then the FPGA application has full read/write access to the LCD." which I have done.

 

NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
assign SF_CE0 = 1;    // Disable Intel StrataFlash
LCD_BUSY.gif
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