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pgigliotti_usac
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Registered: ‎10-22-2020

Looking for XML file for AC701 board with VADJ set to 3.3V(GPIO 16/17 = '1')

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I have an AC701 board that fails to power up when the VADJ select lines (GPIO 16& 17) are programmed to come up as ones, to select 3.3V operation.

I have beat my head on this working through all the TI and Xilinx answer records to resolve this issue (Why these are not jumpers rather than having to jump through all these hoops - ie having to buy a TI USB pod etc.)

Xilinx does provide an "golden" XML file to program the TI devices, but it is for VADJ selected to run at 2.5.  The board is also "supposedly" capable of running with VADJ = 1.8V or 3.3V.  XILINX SHOULD MAKE XML FILES AVAILABLE FOR THESE MODES OF OPERATION AS WELL!!!!  As it is, you have to manually go in an make these changes, with no documentation provided by XiIinx. It is not to terribly difficult, but I may have a bad board, so not having a know solution makes it difficult to rule out user error.

Can anyone (XILINX ????) provide an XML file with the two GPIO in question set high, that is known to work on the board. I have XMLs that I have generated, and that TI has generated, but my board will not power up. It works fine when the XMLs are set up for 1.8V and 2.5V operation.

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pgigliotti_usac
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Registered: ‎10-22-2020

I have two boards that would not communicate via TI POD to Digital Fusion Software.  They connect to the USB but would not detect the TI devices. The FPGA contains the BIST design. I ended up removing Q14, Q15, Q19 and Q20 from one of the boards, and now all communication is working, the boards fully power up and I can monitor voltages via the Fusion Software.

After some trial and error, I changed the VADJ rail settings which were currently set for 2.5 V operation. I used the values from rail 3, which was set to 3.3V, as follows

  1. Click to configure device at address 102,
  2. Click on monitor in the lower left corner
  3. Select Rail #1 in the upper right
  4. Adjust values to match rail 3 (vout, over/under voltage thresholds
  5. Click on Configure in the lower left
  6. change GPIO #1 and #2 to high
  7. Click on store RAM to Flash

I have exported the XML and attached, so that you can just configure the board with this file, as per AR#57452

pgigliotti_usac_1-1610469988251.png

 

pgigliotti_usac_0-1610469944718.png

pgigliotti_usac_2-1610470382971.png

 

 

 

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anatoli
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Registered: ‎06-14-2010

Hello @pgigliotti_usac ,

VADJ voltage is set to 2.5V by default on the KC705/AC701 when shipped to a customer. 
It is possible to change that VADJ within the allowed range if you are interfacing with an FMC card that supports another VADJ value. 
The VADJ value can be changed manually through the TI Fusion Digital Power Designer GUI.
This is the simplest and most convenient way to monitor the voltage and current values for the power rails listed in UG952 (page 65), including VADJ.

You can follow the recommendations and specs in UG952, VCCO_VADJ control on pag.65

https://www.xilinx.com/support/documentation/boards_and_kits/ac701/ug952-ac701-a7-eval-bd.pdf#page=65

I will send you PDF that has steps to change Vadj on KC705 which are similar for AC701. Follow these steps to reprogram VADJ on AC701.

Hope this helps.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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pgigliotti_usac
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Registered: ‎10-22-2020

Anatoli. I am sorry, but there are significant differences between the KC705 and the AC701.  What about the sense resistor selection driven by GPIO16 and GPIO17 on the AC701.  These are not implemented on the KC705! It would be so much simpler if Xilinx would just supply three versions of the XML, for each of the three operating modes!

If you look at page 66 of the user guide that you just mentioned,  It shows the select lines selecting the VADJ voltage.  The PDF you provided does not address this!

Again, can you simply provide the required XML to operate at 3.3V.  I can load that in, just as easily as I can the 2.5V version that Xilinx currently provides.

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travisc
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Registered: ‎10-19-2011

Can you walk us through how you have tried changing it so far? What is your FMC_ADC_SEL line set to? What flow did you use when configuring 1.8v? Did TI provide that file specifically? Are you able to use the TI Fusion software to directly control VCCO VADJ? We do not provide the XML for this, its expected you will need to work with TI for their IC logic and controller if you need guidance on writing the logic to talk with their IC. When you try 3.3v is your FMC connected or not? Do you see a difference in measurement when you FMC card is connected. where are you measuring?

The required steps for the board on xilinx side are documented on page 66 like you mentioned. Sounds like you have the correct voltage selection for 3.3v but you will need to work with TI on validating the code used to reprogram their controller. Do you see any errors, or programing faults for their controller? I dont know that the xilinx forum will be much help with their IC, but i can take a look and see if other users have run into similar issues.

 

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pgigliotti_usac
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Registered: ‎10-22-2020

I start with the board powered off, and plug in the TI pod, then turn on power.  The board fails to power up. Lets ignore that for the moment.  I go into the configuration mode, and see that GPIO 16 and 17 are configured low.  I change them to High, and write to hardware and then NVRAM.  I turn off power.  I unplug the pod and turn on power. The board will not power up.  I turn off the power and plug the pod back in and turn power back on.  Again the board will not power up. I ignore that again, and go to the config selections and see that GPIO 16 and 17 are configured to high.  I change them back to low, write to hardware and NVRAM.  I turn off power, and unplug the cable. I turn power back on, and the board turns on successfully.

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pgigliotti_usac
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Registered: ‎10-22-2020

Any comment.  Is that all I should need to do to set the AC701 board up for VCC Adj for 3.3V operation.  Do I just need to change the GPIO settings, or is anything else required to be changed from the factory default XML?

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pgigliotti_usac
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Registered: ‎10-22-2020

I have two boards that would not communicate via TI POD to Digital Fusion Software.  They connect to the USB but would not detect the TI devices. The FPGA contains the BIST design. I ended up removing Q14, Q15, Q19 and Q20 from one of the boards, and now all communication is working, the boards fully power up and I can monitor voltages via the Fusion Software.

After some trial and error, I changed the VADJ rail settings which were currently set for 2.5 V operation. I used the values from rail 3, which was set to 3.3V, as follows

  1. Click to configure device at address 102,
  2. Click on monitor in the lower left corner
  3. Select Rail #1 in the upper right
  4. Adjust values to match rail 3 (vout, over/under voltage thresholds
  5. Click on Configure in the lower left
  6. change GPIO #1 and #2 to high
  7. Click on store RAM to Flash

I have exported the XML and attached, so that you can just configure the board with this file, as per AR#57452

pgigliotti_usac_1-1610469988251.png

 

pgigliotti_usac_0-1610469944718.png

pgigliotti_usac_2-1610470382971.png

 

 

 

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