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Participant rossetta
Participant
294 Views
Registered: ‎01-09-2014

MCMM/PLL phase relationship between input and output clocks

Dear Xilinx Community,

I am using a MCMM/PLL over KC705 HDL design.

Below is an example of what I am trying to achieve:

1) Let's say I have a input clock frequency clk_in from which with a MCMM I synthesize a clk_out signal requiring phase alignment between clk_in and clk_out. In this configuration, after my MCMM lock signal goes high, I get a fixed phase shift between clk_in and clk_out, I will call this phase shift phi_1.

2) Now let's suppose that for some reason that clk_in is '0' for some time and so clk_out gets '0' as well: so we lose the locked signal of the MCMM.

3) I have my clk_in working again and the MCMM is locked again but the phase relationship between clk_in and clk_out is not phi_1 anymore

 

My question is: what should I do in order to obtain always the same phase shift between clk_in and clk_out upon new MCMM startup even after my MCMM gets reset or signal locked is lost?

 

Thank you in advance,

 

Alessandro

 

 

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1 Reply
Xilinx Employee
Xilinx Employee
250 Views
Registered: ‎06-21-2018

Re: MCMM/PLL phase relationship between input and output clocks

Hi Alessandro,

You mention:

" 3) I have my clk_in working again and the MCMM is locked again but the phase relationship between clk_in and clk_out is not phi_1 anymore

My question is: what should I do in order to obtain always the same phase shift between clk_in and clk_out upon new MCMM startup even after my MCMM gets reset or signal locked is lost?"

Do you mean that the MMCM has been reset and it locked again?
As described on page 79 of UG472: "The MMCM must be reset after LOCKED is deasserted."

Once the MMCM has been reset, you should have the desired phase once it locks again.

Thanks,
Andres