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744 Views
Registered: ‎03-15-2017

MIG DDR3 init_calib_complete not go high on KC705 board

Hi,

 I used the MIG DDR3 softcore to communcation with KC705 on board ddr3,the simulation is ok ,but the init_calib_complete never go to high when I on board.

 I have checked the mmcm_locked is high,and the Initialization signals are ok as well(attached as below).

 Now i post some information about the design configure.

  a) tool  

     software:Vivado 2016.1

     hardware KC705

  b)MIG configure

     

    1) Create Design, 1 controller, with AXI interface

 

    2) no pin compatible FPGAs

 

    3) Select DDR3 SDRAM

 

    4) Clock period: 1250ps (800 Mhz)

      PHY to Controller Clock Ratio: 4:1

      Components: SODIMMs

      Part: MT8 JTF 128 64Hz - 1G6

      Ordering: Normal

 

   5) AXI datawidth: 64

     Arbitration Scheme: WRITE_PRIORITY

     ID Width: 4

 

   6) Input Clock period: 5000ps (200Mhz)

     Read Burst Type: Sequential 

     Output Driver Impedance Control: RZQ/7

     Controller Chip Select Pin: Disable

     RTT - On Die Termination: RZQ/6 

 

   7) System Clock: No buffer

     Reference Clock: No buffer

     Reset Polarity: Active Low

     added debug signals for 1024

     XADC Instantiation= ENABLED

   8) DCI Cascade = checked

   9)Pinout know is fixed

 c)hardware configure

  1)clock:KC705 system differential clock input(200MHz) ,use IBUFGDS to give it to sys_clk_i and clk_ref_i

  2)reset: use the Dip switch as the sys_rst_n(low active),and checked the ddr3_reset_n state with the led is ok.

  

  below is the ILA capture data for ddr3_initialization signals:

dqs_found.png

 rdlvl.png

 

 wrcalpng.png

wrlvl.png

时序约束.png

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
623 Views
Registered: ‎06-30-2010

Re: MIG DDR3 init_calib_complete not go high on KC705 board

before doing all of this debug please use the ready to download bitfile from the KC705 page and verify that the board is functioning correctly

https://www.xilinx.com/products/boards-and-kits/kcu105.html
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