when I generate a DDR2 controller core, the pin assignments created in the UCF file do not correspond to the master UCF pin constraints, found here: http://www.xilinx.com/products/boards/ml505/docs/ml50x_U1_fpga.ucf. The pin assignments from the reference ML505 MIG Design also do not make sense (for example, NET "ddr2_a" LOC = "N32" ; however, according to the ML505 User Guide, N32 connects to HDR2_10, while the "real" DDR2_A9 pin is R28).
What did I do wrong? Can I automatically correct the generated pin assignments, or do I have to enter them manually (i.e., copy them from the master UCF file and adjust net names)?
Thanks for your help,
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