01-16-2010 10:33 AM
I have a relatively high-frequency (16MHz) signal that I need to input to the global clock network on a ML506 development board. The clock signal that I am using is rated to drive a 24pF load. I need to know whether or not I will need to buffer the clock signal in order to use it as a clock input. I am currently using the XGI expansion headers (FPGA pin G15, header J5 pin 27) as my clock input. That's the only one I can find on the XGI headers that is connected to the GC network.
Where can I find information about load capacitance on the ML50X inputs? Or should I be using some other input for my clock?
01-18-2010 10:22 AM
01-18-2010 12:14 PM
Thank you for your reply.
What about the DC characteristics for the ML50X platforms? Since there's a fairly long trace from the FPGA pin to the output on the development board and other nearby components inducing some parasitic capacitance, I would assume that it would be more than the 8pF load specified in the V5 datasheet.