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Visitor
Visitor
4,626 Views
Registered: ‎07-10-2008

ML505/ML506/ML507 Input Load Capacitance

I have a relatively high-frequency (16MHz) signal that I need to input to the global clock network on a ML506 development board. The clock signal that I am using is rated to drive a 24pF load. I need to know whether or not I will need to buffer the clock signal in order to use it as a clock input. I am currently using the XGI expansion headers (FPGA pin G15, header J5 pin 27) as my clock input. That's the only one I can find on the XGI headers that is connected to the GC network.

 

Where can I find information about load capacitance on the ML50X inputs? Or should I be using some other input for my clock?

 

Thank you,

LE

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Xilinx Employee
Xilinx Employee
4,597 Views
Registered: ‎01-03-2008

Re: ML505/ML506/ML507 Input Load Capacitance

The input pin capacitance for Virtex-5 is listed in Table 3 of the datasheet (8pF).
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Visitor
Visitor
4,592 Views
Registered: ‎07-10-2008

Re: ML505/ML506/ML507 Input Load Capacitance

Thank you for your reply.

 

What about the DC characteristics for the ML50X platforms? Since there's a fairly long trace from the FPGA pin to the output on the development board and other nearby components inducing some parasitic capacitance, I would assume that it would be more than the 8pF load specified in the V5 datasheet.

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