ML507 AD9980 I2C bus

[likeyou614]

i used AD9980 in ml507 evaluation board, i took the vga input from the computer, the resolution is 800x600 in 60 Hz,
from the datasheet,i change the register values accordingly using i2c,, But i2c writes register seem unsuccessful  .

Could you tell me that there is an example, is that all right to let me consult? thank ...

 E_Mail:yzliao@j92a21.ee.ncku.edu.tw

PS: ML507 datasheet : I2C write slave address=0X4C

       AD9980 datasheet: I2C write slave address=0X98 

       Is that correct?  

[miggae]

Hi,

I ran into such issue on my "old" ML507 board, i.e. all IIC writes worked fine for all IIC devices except for the AD9980 ... After changing the ADC's IIC address from 0x4C (acc to Xilinx ML507 doc) to 0x4D, it worked fine.

On all "new" ML507 boards which I bought later on, the ADC's I2C address is at the "Xilinx-specified" address 0x4C.

Hope this solves your issue.

Cheers,

BTW, 0x4C is 0x98 divided by 2 .... so there is a relationship.

[tannous]

miggae,

Can you please tell me what are the registers that you are writing to and the corresponding values?

I tried to write to registers 0x01 and 0x02 the values 0x32 and 0x00 for 640x480 @ 60 Hz with no luck so far.

The remaining registers are left at the default value.

Thank you,

T.

[miggae]

Hi Tannous

Below, there are the ADC registers "writes" of a working example on ML507.

First, you'll find general initialisation values to be written at the beginning. After that, do write the monitor timing dependent register values (which I appended for 3 different resolutions: VGA, SVGA, XGA).

Best

Miggae

// Initialize AD9980

   0x1E, 0xA4 // Input and Power Control // 9980
  ,0x1F, 0x14 // Output_Control {[7:5]=output_mode, [4]=primary_out_en,[3]=secondary_out_en,[2:1]=drive_strength,[0]=clk_inv}   // 9980
  ,0x20, 0x01 // Output Select 2
  ,0x05, 0x40 // Red Gain
  ,0x06, 0x00
  ,0x07, 0x40 // Green Gain
  ,0x08, 0x00
  ,0x09, 0x40 // Blue Gain
  ,0x0A, 0x00

  ,0x1B, 0x33 // Clamp and Offset (auto-offset every 64 clamps)

  ,0x0B, 0x02 // Red Offset  
  ,0x0C, 0x00
  ,0x0D, 0x02 // Green Offset  
  ,0x0E, 0x00
  ,0x0F, 0x02 // Blue Offset  
  ,0x10, 0x00

  ,0x18, 0x00
  ,0x12, 0x80 // Hsync control

  //analog 640x480P60 (VGA)
   0x01, 0x32 // PLL_div_msb {[7:0]=pll_div[11:4] }    // 800
  ,0x02, 0x00 // PLL_div_lsb {[7:4]=pll_div[3:0] }     // 800
  ,0x03, 0x48 // Clk_Gen_Ctrl {[7:6]=vco_range, [5:3]=charge_pump_current, [2]=ext_clk_en}
  ,0x04, 0xA0 // Phase_Adjust {[7:3]=phase_adjust}
  ,0x12, 0x10 // Hsync Control {...,[3]= hsync_out polarity} 
  ,0x13, 0x60 // Hsync_Duration {[7:0]= hsync_pulsewidth_duration }
  ,0x14, 0x10 // Vsync Control {...,[3]= vsync_out polarity}
  ,0x19, 0x04 // Clamp_Placement {[7:0]= clamp_placement }  
  ,0x1A, 0x1A // Clamp_Duration {[7:0]= clamp_duration}

  //analog 800x600P60 (SVGA)
  ,0x01, 0x42 // PLL_div_msb {[7:0]=pll_div[11:4] }   
  ,0x02, 0x00 // PLL_div_lsb {[7:4]=pll_div[3:0] } 
  ,0x03, 0x48 // Clk_Gen_Ctrl {[7:6]=vco_range, [5:3]=charge_pump_current, [2]=ext_clk_en}  
  ,0x04, 0x80 // Phase_Adjust {[7:3]=phase_adjust}
  ,0x12, 0x18 // Hsync Control {...,[3]= hsync_out polarity} 
  ,0x13, 0x80 // Hsync_Duration {[7:0]= hsync_pulsewidth_duration }
  ,0x14, 0x18 // Vsync Control {...,[3]= vsync_out polarity}
  ,0x19, 0x04 // Clamp_Placement {[7:0]= clamp_placement }  
  ,0x1A, 0x3C // Clamp_Duration {[7:0]= clamp_duration}

  //analog 1024x768P60 (XGA)
  ,0x01, 0x54 // PLL_div_msb {[7:0]=pll_div[11:4] }   
  ,0x02, 0x00 // PLL_div_lsb {[7:4]=pll_div[3:0] } 
  ,0x03, 0xA8 // Clk_Gen_Ctrl {[7:6]=vco_range, [5:3]=charge_pump_current, [2]=ext_clk_en}  
  ,0x04, 0x80 // Phase_Adjust {[7:3]=phase_adjust}
  ,0x12, 0x10 // Hsync Control {...,[3]= hsync_out polarity} 
  ,0x13, 0x88 // Hsync_Duration {[7:0]= hsync_pulsewidth_duration }
  ,0x14, 0x10 // Vsync Control {...,[3]= vsync_out polarity}
  ,0x19, 0x04 // Clamp_Placement {[7:0]= clamp_placement }  
  ,0x1A, 0x20 // Clamp_Duration {[7:0]= clamp_duration}

[likeyou614]

 HI,miggae.

Do you use verilog simulation i2c bus? 

i use Ad9980 in ml507 board . I2c writes register seem unsuccessful.

I use register that you offered  the ADC registers "writes" of a working example on ML507

I2c writes register seem unsuccessful.

i used AD9980 in ml507 evaluation board, i took the vga input from the computer, the resolution is 800x600 in 60 Hz,from the datasheet,i change the register values accordingly using i2c,
however, pixel clock is 50 mhz (40 mhz required) and hsout is incorrect but vsout is correct.
when i changed the resolution and frequency to any value, the pixel clock and hsout does not change, i do not know where is the problem.
why doesn’t the pixel clock change?

i do not give any external clock to the device, also on board oscillator frequency is 100 Mhz,
and i am sure about external clock (at least i program according to the given register values to use internal clock which is written in the datasheet ),
i do not understand the situation: when pixel clock and hsout won’t  correct timings, how can vsout correct timing?

any experience or suggestions?

Can you send your example to me? 

please help me ...

thanks...

[miggae]

Hi likeyou614

I double-checked the registers and AD9980 documentation and found 2 mistakes, hope this solves the problem.

  //analog 640x480P60 (VGA)
  ,0x03, 0x60 // Clk_Gen_Ctrl {[7:6]=vco_range, [5:3]=charge_pump_current, [2]=ext_clk_en}

  //analog 800x600P60 (SVGA) 
  ,0x03, 0x60 // Clk_Gen_Ctrl {[7:6]=vco_range, [5:3]=charge_pump_current, [2]=ext_clk_en}   

Cheers

miggae

ps:

I've been working with EDK Video Starter Kit Reference Design for Spartan3DSP which I ported to ML507.

[tannous]

Thank you Miggae!

[hyzr]

Dear likeyou 614 and miggae ,

       I am a starter in FPGA design. and my tuitor told me to design a demo about VGA in and DVI out.My idea is capture the RGB data from the ad9980 writing into  the ddr2 sdram and then sending the data to CD7301C(DVI out).I have some troubles to set the regisiters.Can you give me the completed project about VGA in as reference.I think i cannot  complete the other part of my demo--DVI out without your help.

thanks.

Email:hyzr@shu.edu.cn

[likeyou614]

The control of my adc ad9980 has not succeeded yet!
I listen to the opinion of miggae, am trying to use edk,
Produce iic signal to control ad9980, and also in study!
Hope miggae can be sent for my reference too!
Thanks! 

E_mail:yzliao@j92a21.ee.ncku.edu.tw

[miggae]

Hi

I am going to send to both of you an older ML507-migrated VSK (Video Starter Kit) Reference Design which was originally done by Xilinx for Spartan3-Dev-Boards.

It reads VGA-800x600@60 input, saves video data into DDR2 and sends it to DVI-output (CH7301C), Xilinx calls it the "Framebuffer" application.

Because we exchanged the AD9980 on ML507 with a AD9983A-170, all the optimised ADC configuration parameters of my latter/current designs will not be of any use to you.

Best,
miggae

[hyzr]

Thank you very much! I think i'll do my best to  complete this demo.l 'll share the project with everyone as soon as possible.

[yoavfreund]

In case this helps anyone, I figured out how to initialize the Chrontel CF7301C-TF and the AD9980 on the ML506 board to do 640x480 VGA in to DVI out. You can use the ML506 IP STD Cores base system as an example. Look at any of the IIC applications and use as a model to write your own (based on instantiating an XPS_IIC core of your own, in your own system). Bring in the SDA_VIDEO and SCL_VIDEO pins from off chip (by editing the system ucf and mhs). Route them to the SDA and SCL inputs on the XPS_IIC core. Then replace the IIC app's read example with the following:

    Xuint16 StatusReg;

    /*
     * Make sure all the Fifo's are cleared and Bus is Not busy.
     */
    do {
         StatusReg = XIo_In8(XPAR_IIC_0_BASEADDR + XIIC_SR_REG_OFFSET);
         StatusReg = StatusReg & (XIIC_SR_RX_FIFO_EMPTY_MASK | XIIC_SR_TX_FIFO_EMPTY_MASK | XIIC_SR_BUS_BUSY_MASK);
    }
    while (StatusReg != (XIIC_SR_RX_FIFO_EMPTY_MASK | XIIC_SR_TX_FIFO_EMPTY_MASK));


    Xuint8 DVIReg0[]    = {0x21, 0x09 };
    Xuint8 DVIReg1[]    = {0x1D, 0x43 };
    Xuint8 DVIReg2[]    = {0x23, 0x08 };
    Xuint8 DVIReg3[]    = {0x48, 0x18 };
    Xuint8 DVIReg4[]    = {0x49, 0xC0 };
    Xuint8 DVIReg5[]    = {0x33, 0x08 };
    Xuint8 DVIReg6[]    = {0x34, 0x16 };
    Xuint8 DVIReg7[]    = {0x35, 0x70 };
    Xuint8 DVIReg8[]    = {0x36, 0x60 };

    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, DVI_IIC_ADDRESS, DVIReg0, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, DVI_IIC_ADDRESS, DVIReg1, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, DVI_IIC_ADDRESS, DVIReg2, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, DVI_IIC_ADDRESS, DVIReg3, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, DVI_IIC_ADDRESS, DVIReg4, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, DVI_IIC_ADDRESS, DVIReg5, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, DVI_IIC_ADDRESS, DVIReg6, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, DVI_IIC_ADDRESS, DVIReg7, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, DVI_IIC_ADDRESS, DVIReg8, 2, XIIC_STOP) != 2)
        return XST_FAILURE;


    Xuint8 VGAReg0[]    = {0x01, 0x32 };
    Xuint8 VGAReg1[]    = {0x02, 0x00 };
    Xuint8 VGAReg2[]    = {0x03, 0x60 };
    Xuint8 VGAReg3[]    = {0x04, 0x80 };
    Xuint8 VGAReg4[]    = {0x05, 0x40 };
    Xuint8 VGAReg5[]    = {0x06, 0x00 };
    Xuint8 VGAReg6[]    = {0x07, 0x40 };
    Xuint8 VGAReg7[]    = {0x08, 0x00 };
    Xuint8 VGAReg8[]    = {0x09, 0x40 };
    Xuint8 VGAReg9[]    = {0x0A, 0x00 };
    Xuint8 VGAReg10[]    = {0x0B, 0x00 };
    Xuint8 VGAReg11[]    = {0x0C, 0x80 };
    Xuint8 VGAReg12[]    = {0x0D, 0x00 };
    Xuint8 VGAReg13[]    = {0x0E, 0x80 };
    Xuint8 VGAReg14[]    = {0x0F, 0x00 };
    Xuint8 VGAReg15[]    = {0x10, 0x80 };
//    Xuint8 VGAReg16[]    = {0x18, 0x00 };
    Xuint8 VGAReg17[]    = {0x19, 0x04 };
    Xuint8 VGAReg18[]    = {0x1A, 0x1A };
    Xuint8 VGAReg19[]    = {0x1B, 0x3B };
    Xuint8 VGAReg20[]    = {0x1C, 0x80 };
//    Xuint8 VGAReg21[]    = {0x12, 0x10 };
    Xuint8 VGAReg22[]    = {0x13, 0x60 };
//    Xuint8 VGAReg23[]    = {0x14, 0x10 };
//    Xuint8 VGAReg24[]    = {0x1E, 0xB4 };
//    Xuint8 VGAReg25[]    = {0x1F, 0x94 };
//    Xuint8 VGAReg26[]    = {0x20, 0x05 };
    Xuint8 VGAReg27[]    = {0x2D, 0xE8 };
    Xuint8 VGAReg28[]    = {0x2E, 0xE0 };

    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg0, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg1, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg2, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg3, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg4, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg5, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg6, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg7, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg8, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg9, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg10, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg11, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg12, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg13, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg14, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg15, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
//    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg16, 2, XIIC_STOP) != 2)
//        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg17, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg18, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg19, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg20, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
//    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg21, 2, XIIC_STOP) != 2)
//        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg22, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
//    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg23, 2, XIIC_STOP) != 2)
//        return XST_FAILURE;
//    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg24, 2, XIIC_STOP) != 2)
//        return XST_FAILURE;
//    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg25, 2, XIIC_STOP) != 2)
//        return XST_FAILURE;
//    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg26, 2, XIIC_STOP) != 2)
//        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg27, 2, XIIC_STOP) != 2)
        return XST_FAILURE;
    if (XIic_DynSend(XPAR_IIC_0_BASEADDR, VGA_IIC_ADDRESS, VGAReg28, 2, XIIC_STOP) != 2)
        return XST_FAILURE;

On the ML506, the DVI_IIC_ADDRESS and VGA_IIC_ADDRESS values are:

#define DVI_IIC_ADDRESS 0x76
#define VGA_IIC_ADDRESS 0x4C

Note that the comment out lines do in fact need to be commented out (or removed) for the initialization to complete correctly.

Good luck.

Matt

[ravi12]

hi

i have an ml507 borad and a ptz evi-d70 sony camera.

i want to connect this camera with the ml507 board. it has an

video input port. i don't have any idea as how to connect.

plz help me and tell me the exact requirements.

regards

ravi 

[jiangweihui]

i used AD9980 in ml507 evaluation board, i took the vga input from the computer, the resolution is 800x600 in 85Hz, from the datasheet,i change the register values accordingly using i2c,, But i2c writes register seem unsuccessful . Could you tell me that there is an example, is that all right to let me consult? thank ...

[jiangweihui]

who can help me

[jiangweihui]

i used AD9980 in ml507 evaluation board, i took the vga input from the computer, the resolution is 800x600 in 85Hz, from the datasheet,i change the register values accordingly using i2c,, But i2c writes register seem unsuccessful . Could you tell me that there is an example

EMAIL:superjwh@126.com

[sneuhold]

Hi Miggae,

Would it be possible for you to send me this design also? Just the unoptimised version as described below is fine. I just need a place to start.

thanks,

Stephan

stephan.neuhold@nuhorizons.com

[shashwat]

Hi all,

I have 2 queries basically

1) Just like the Chrontel DVI chip do we need to send a signal similar to net_vcc to power on the AD 9980 ADC chip on board in front of the VGA port of the ML507 board.

2) Also to check whether the ADC has been correctly configured and working for my video system, the only way to check is to take the incoming data i.e. the RGB signals and the sync signals from the ADC and then send it to the display. Do we need a memory buffer here? if yes then we plan to use the DDR RAM as the video frames memory. From the ddr ram we need to take the data to the xps_tft IP we have used. How do we achieve sending the RGB data which have arrived at the FPGA pins (as specified by the ucf to connect adc to fpga) to the DDR RAM memory.???

Regards,

Shashwat.

[lidaxjtu]

can you send me the design of vga input ,or some helpful design.

thanks.       lida1204@gmail.com

[awattar]

Can anyone kindly send me a working design of of VGA input, or the ported design from the Spartan video kit.?

Thanks  a lot  :smileyhappy:

az_wattar @ hotmail.com

[eteam00]

Is this thread the 'lost souls of FPGA design' magnet, or what?

-- Bob Elkind

[lidaxjtu]

you can refer to the design framebuffer in ug456.rar

[lidaxjtu]

I created a simple framebuffer demo 640x480P60 for ug456 to ml510, you should synthesize it;

and you can modify the input vga config and output dvi config for other screen size, refer to the code of ug456 and datasheets of the two chips. wish you work well.

[jaesung.lee]

Thank you so much

It definitely helps me understand and develop futher

PS: For other's infomation, ML507 user must change the device name into xc5vfx70t and then synthesize it