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ML507 board - SDRAM data lost on reprogram of FPGA

I have a program which stores data on the ML507's SDRAM (DDR2 SODIMM).  At some point in my application, I mimic a severe failure that would require a reload of the FPGA bitstream.  I reload via the Program FPGA command in the SDK.  I would expect that this process resets the V5, re-downloads the bitstream with the application in it and starts up my application again.  However, it also seems to be resetting the SDRAM since when I read the stored data from prior to the re-program, it's now garbage.  Is this a function of the board, or something in the processor or memory interface? 


I'm using a PPC440 with the MPMC to access the SODIMM.  The processor reset module has a peripheral reset that connects to the MPMC, but again I don't see that reset being passed along to the SODIMM, so I'm unclear why that chip is getting reset.  Nothing on the schematic shows a reset line to the SODIMM either.

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Xilinx Employee
Xilinx Employee
Registered: ‎10-23-2007

Your data could change for at least these two reasons:


- during the reprogram of the FPGA, there is no refresh being issued to the DRAM, so the DRAM will lose data

- the calibration process of the FPGA phy may be overwriting your data



Registered: ‎02-27-2008

What is it about "dynamic memory" that you do not understand?

Without refresh, the data just leaks away,
Austin Lesea
Principal Engineer
Xilinx San Jose
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