We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor ashlesha1
Registered: ‎02-20-2008

ML605 DDR3 write and read data mismatch



We are using ML605 board for our application and MIG reference design DDR3 controller to write and read into DDR3 memory.

Since months we have a design which is issuing commands and data to MIG controller. The commands are issued at a slow pace and the design is working perfectly on board.


Now with our new requirement, we have to make our design more quick and efficient, so we have tried to issue back-to-back commands to the memory controller. So, we are giving back-to-back write commands first, ofcourse with the data and when the writing is completed, we are then issuing back-to-back read commands for the same addresses. Please note that we are wriitng into consecutive locations of memory. Burst length selected is 8 so we are increment the user address by 8 every time we give the command.

But, while reading we are not getting the same data as we have written into the memory. The read data is from some random address.

The design is working properly in simulation but on board we are not getting the data as expected. Please find the attached chipscope waveform in VCD format. Don't know if this will be useful to debug.


Please help!!!!

Tags (2)
0 Kudos