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Observer fruntxas
Observer
6,422 Views
Registered: ‎10-07-2009

ML605 Led Testing by Hardware Co-Simulation

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To whom it may concern,

 

I recently bought a ML605 kit from AVNET and I'm trying make a simple LED test controlled by the switches

I get no errors performing a JTAG compilation, but the board(leds) don't light up in any way.

 

I attached my file hoping someone can help :(

Got a counter and inverter on the left side of the Gateway Ins but those don't really matter.

 

Cheers,

 

Tiago

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1 Solution

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Xilinx Employee
Xilinx Employee
8,089 Views
Registered: ‎11-28-2007

Re: ML605 Led Testing by Hardware Co-Simulation

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First of all, it's better to post SysGen related questions on the DSP Tools board.

 

You need to create non memory mapped (NMM) ports for gateway ins and outs that talk to the physical pins during hardware co-simulation. Please check the blog below on how to create NMM ports:

 

SysGen: Create New HWCOSIM Target with NMM Ports

 

 


@fruntxas wrote:

Hi bwiec,

 

Regarding the LOC constraints you are right. They were in the folder you refered.

 

Regarding the setup. I think I can just drag it to the design and run it. 

With both Gateway Ins mapped onto 2 switches and Gateway Outs mapped onto LEDs does it really make a difference?

Even tried hooking up both library inputs to the Gateway Ins outputs but nothing happens 

 

 

I have no issue running a Co-Simulation of the DUC/DDC example (xapp1018 updated to Virtex-6).

But if I map a gateway out to a single led, nothing comes out.




Cheers,
Jim

View solution in original post

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6 Replies
Explorer
Explorer
6,411 Views
Registered: ‎04-09-2008

Re: ML605 Led Testing by Hardware Co-Simulation

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Have you tried running the built-in-self-test (BIST) examples to make sure it's not a hardware problem? You run it from the CF card that came with the kit.
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Observer fruntxas
Observer
6,409 Views
Registered: ‎10-07-2009

Re: ML605 Led Testing by Hardware Co-Simulation

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I did.

 

The test passes without any problem.

 

Currently compiling the SysGen Example with the DUC/DDC, but added an extra gateway out with a led mapped.


Let's see what comes out.

 

 

When I open the Project file generated by the Hardware Co-Simulation the ucf only has two lines (regarding my example):

 

# Global period constraint
NET "clk" TNM_NET = "clk_c1008a90";
TIMESPEC "TS_clk_c1008a90" = PERIOD "clk_c1008a90" 20.0 ns HIGH 50 %;

 

 

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Xilinx Employee
Xilinx Employee
6,402 Views
Registered: ‎08-02-2011

Re: ML605 Led Testing by Hardware Co-Simulation

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I think you're looking at the wrong .ucf

 

Have a look in the ./netlist/sysgen folder and you will see your LOC constraints

 

When you generate your hw co-sim library, how are you hooking up the block to actually run the co-sim?

 

I would suggest going through the hw co-sim chapter in the System Generator Users Guide (UG640) Chapter 3

www.xilinx.com
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Observer fruntxas
Observer
6,394 Views
Registered: ‎10-07-2009

Re: ML605 Led Testing by Hardware Co-Simulation

Jump to solution

Hi bwiec,

 

Regarding the LOC constraints you are right. They were in the folder you refered.

 

Regarding the setup. I think I can just drag it to the design and run it. 

With both Gateway Ins mapped onto 2 switches and Gateway Outs mapped onto LEDs does it really make a difference?

Even tried hooking up both library inputs to the Gateway Ins outputs but nothing happens 

 

 

I have no issue running a Co-Simulation of the DUC/DDC example (xapp1018 updated to Virtex-6).

But if I map a gateway out to a single led, nothing comes out.

0 Kudos
Xilinx Employee
Xilinx Employee
8,090 Views
Registered: ‎11-28-2007

Re: ML605 Led Testing by Hardware Co-Simulation

Jump to solution

First of all, it's better to post SysGen related questions on the DSP Tools board.

 

You need to create non memory mapped (NMM) ports for gateway ins and outs that talk to the physical pins during hardware co-simulation. Please check the blog below on how to create NMM ports:

 

SysGen: Create New HWCOSIM Target with NMM Ports

 

 


@fruntxas wrote:

Hi bwiec,

 

Regarding the LOC constraints you are right. They were in the folder you refered.

 

Regarding the setup. I think I can just drag it to the design and run it. 

With both Gateway Ins mapped onto 2 switches and Gateway Outs mapped onto LEDs does it really make a difference?

Even tried hooking up both library inputs to the Gateway Ins outputs but nothing happens 

 

 

I have no issue running a Co-Simulation of the DUC/DDC example (xapp1018 updated to Virtex-6).

But if I map a gateway out to a single led, nothing comes out.




Cheers,
Jim

View solution in original post

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Observer fruntxas
Observer
6,376 Views
Registered: ‎10-07-2009

Re: ML605 Led Testing by Hardware Co-Simulation

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Sorry about the wrong location.

 

The blog helped me a lot and I can do what I wanted.

 

Thanks a lot jimwu ;)

 

Cheers

 

Tiago

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