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Visitor
Visitor
9,941 Views
Registered: ‎03-22-2011

ML605 Virtex6 GTX Transceiver

Hi,

 

I have two ML605 boards with V6. I want to test GTX transceivers, and I connected them with SMA cables (J26 - J29 connectors). Then, I generated IBERT core, downloaded the same design on both boards, and then I checked in Chipscope the signals. Everytnihg seems OK because the BER is zero. 

 

 

After that, I generated an example design with CoreGen, and downloaded the example on both boards. When I checked the signals in the Chipscope, I saw that BER is not zero :(

 

When I use that example only to one board, and create a loopback with SMA cables, everything works fine (BER=0)

 

So, my question: Has anyone tried that GTX coregen example on two boards?

 

Best regards,

Darko T.

 

P.S. I have 12.4 ISE

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Xilinx Employee
Xilinx Employee
9,930 Views
Registered: ‎01-03-2008

The IBERT core is a very complex core that enables a wide range of configuration.  One feature IBERT is that it clocks all of the receiver checking logic from the RX recovered clock and this allows the design to function with different reference clock sources (one on each ML605 board).

 

The GTX example design is a very simple exampe and uses the same clock for both the TX and RX data ports.  This design requires that the same clock source is used for both ends of the link or a higher level protocal (such as Aurora, Ethernet, PCIE...) implements 8B10B encoding and clock correction.  This is why you are getting bit errors.

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Visitor
Visitor
9,897 Views
Registered: ‎03-22-2011

Thank you. I'll try it.

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Visitor
Visitor
9,435 Views
Registered: ‎06-07-2012

in order to improve BER, probably one needs to run sweep test on tab 3

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