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Visitor harishk91
Visitor
10,038 Views
Registered: ‎01-19-2014

Maximum Single ended Clock Frequency Supported by FMC

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Hi,

 

I'm Developing a custom FMC daughter Board for KC705,

I'm using AD9772a (Analog devices DAC) the Data level required for DAC is LVTTL 3.3V so i'm setting VADJ to 3.3V.

To synchronise data with the clock, the DAC outputs a Clock signal (3.3V, 80MHZ-100MHz, SIngle Ended) which has to be fed to FPGA thro FMC connector. We planned to use a sigle ended to differential conversion IC(ADN4663.), but the output of this IC (ADN4663) is LVDS25, since i'm making VADJ = 3.3V ,is it possible to have LVDS25 thru the FMC connector?

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1 Solution

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Moderator
Moderator
16,781 Views
Registered: ‎01-15-2008

Re: Maximum Single ended Clock Frequency Supported by FMC

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check the table 1-55 in the selectio user guide for LVDS_25 VCCo requirements for the input and output.

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

you need to particularly look at the notes 1 of this table and follow when you are providing lvds_25 input when the vcco is not 2.5v.

 

--Krishna

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4 Replies
Moderator
Moderator
16,782 Views
Registered: ‎01-15-2008

Re: Maximum Single ended Clock Frequency Supported by FMC

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check the table 1-55 in the selectio user guide for LVDS_25 VCCo requirements for the input and output.

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

you need to particularly look at the notes 1 of this table and follow when you are providing lvds_25 input when the vcco is not 2.5v.

 

--Krishna

View solution in original post

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Visitor harishk91
Visitor
10,013 Views
Registered: ‎01-19-2014

Re: Maximum Single ended Clock Frequency Supported by FMC

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Thanks for the Quick Reply,

So It means i can input LVDS_25 to a HR bank which is Power by VCCO=3.3V, but i can't Output LVDS_25 from the HR bank Powered by VCCO=3.3V?

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Instructor
Instructor
10,005 Views
Registered: ‎08-14-2007

Re: Maximum Single ended Clock Frequency Supported by FMC

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First of all, LVDS has a common-mode voltage of 1.2V regardless of the Vcco that powers it.  So the actual signals at the board level are just LVDS, not LVDS_25 or LVDS_33.  Any combination of chips with different power-supply voltages can interoperate using the LVDS standard.  The important thing is that the standard used by the FPGA matches the actual voltage supplied to that bank.  This is very different from LVCMOS, which drives from rail-to-rail and therefore depends on the bank voltage. 

 

LVDS receivers are basically differential voltage comparators designed to operate near 1.2V, but which usually can handle a larger common-mode voltage range.  For Xilinx parts, you need to be sure that the overall swing on the LVDS inputs doesn't include the positive voltage rail or ground.  Otherwise you will activate the clamp diodes.  Depending on the part you use, the LVDS receiver may be powered by Vcco or by Vccaux.  However the input clamp diodes always go to Vcco.  Thus in a part with LVDS receivers powered by Vccaux you could have many different Vcco's but not for example 1.2V which would clamp the positive half of the signal swing.  Also note that some families require a particular bank Vcco in order to power the differential input terminators.

-- Gabor
Visitor harishk91
Visitor
9,988 Views
Registered: ‎01-19-2014

Re: Maximum Single ended Clock Frequency Supported by FMC

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Thank you for the suggestion Gabor.

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