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Observer
Observer
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Registered: ‎07-13-2017

MicroBlaze on VCU108 Example

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My Background:

I have seen a number of microblaze examples, and I have done some on the Zynq series chips.  I have a VCU108 that I thought I would be able to utilize over PCI, but that's proven too much for this hobbiest. :-)  [I have a computer Science background, with 25 yrs development, and some experience with smaller FPGA].  So I know a little and trying to learn.

 

My Goal:

So for now I want to switch to what I know.  I'm looking to use microblaze environment to build the hardware elements, then use the SDK to write software to exercise the hardware.

 

My baseline design is one that can be found on youtube. 

https://www.youtube.com/watch?v=5awHRI898Rg 

 

It builds a simple MB with UART, to display Hello World.

 

My Current problem:

 

I'm left trying to map the XDC.  I downloaded the XDC for the VCU108 board and I came up witht he following:

set_property PACKAGE_PIN BC24     [get_ports "rs232_uart_txd"] ;# Bank  94 VCCO - VCC1V8_FPGA - IO_T0U_N12_94
set_property IOSTANDARD  LVCMOS18 [get_ports "rs232_uart_txd"] ;# Bank  94 VCCO - VCC1V8_FPGA - IO_T0U_N12_94
set_property PACKAGE_PIN BE24     [get_ports "rs232_uart_rxd"] ;# Bank  94 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_94
set_property IOSTANDARD  LVCMOS18 [get_ports "rs232_uart_rxd"] ;# Bank  94 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_94

set_property PACKAGE_PIN E36      [get_ports "reset"] ;# Bank  49 VCCO - VCC1V2_FPGA - IO_T1U_N12_49
set_property IOSTANDARD  LVCMOS12 [get_ports "reset"] ;# Bank  49 VCCO - VCC1V2_FPGA - IO_T1U_N12_49

set_property PACKAGE_PIN R32      [get_ports "clock_rtl"] ;# Bank  48 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_48

create_clock -period 20.000 -name clock_rtl [get_ports "clock_rtl"]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

That provided a slew of Critical Warnings during implementation.  Then I commented it all out and the warnings went away.  This makes me think if I select the Board, that at some point the ports in the IP Block Design automatically get assign.  Is that correct?

 

After Synthesizinf and Implementing, I generate the bitstream I get the following two errors:

[DRC NSTD-1] Unspecified I/O Standard: 1 out of 4 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clock_rtl.

and

[DRC UCIO-1] Unconstrained Logical Port: 1 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: clock_rtl.

They are both associated with colck_rtl.  The second looks to be because it is not constrained to a location.  This would lead me to believe that I need to have an entry in the XDC for it.   

 

So I'm just a little bit confused here.

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Observer
Observer
5,350 Views
Registered: ‎07-13-2017

I figured outthat if I specify the board I don;t need to define anything in the XDC.

View solution in original post

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Observer
Observer
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Registered: ‎07-13-2017

I found an example that walks me through this.  Its not as straight forward as using the Zynq PS but it'll do.

 

MicroBlaze Overview:

https://www.youtube.com/watch?v=p3DIKNMlfHM

 

Building up the IP Blocks and using the SDK:

https://www.youtube.com/watch?v=VjYdNIOyRcE 

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Observer
Observer
5,351 Views
Registered: ‎07-13-2017

I figured outthat if I specify the board I don;t need to define anything in the XDC.

View solution in original post

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