I need to use DMA in one of my projects so in order to get used to it I implemented a simple system with a 32-bit counter connected to a FIFO from which the DMA is reading the values using AXI stream interface. The block diagram of the test module is in attach. The problem is with the sequence of the counting. I am invalidating the cache to make sure I am reading the updated values from the memory. At the beginning the system works fine and it displays the counting sequencing correctly. However, after 60000 reads from the DMA, there are some counting values that are missing (images attached).
I am not sure what might be causing the problem. My best guess would be the DMA not being fast enough and because of that, the FIFO is being rewritten in positions that were still not read by the DMA. However I find it odd that this only happens in approximatelly 142 postitions (the number of counting values skipped). But the problem is systematic. It always happens after 60000 reads. I am running the FIFO and DMA with the same clock frequency. The FIFO has 4096 bytes and I am reading packages of 1024 bytes with the DMA.
Any thoughts on what might be causing this behavior? Have you guys had this problem before?