07-21-2019 08:13 AM
Currently using Vivado 2017.4 with Zynq7000 FPGA but need 2 things :
-> a free VHDL linting tool to check the VHDL for any issues before running RTL or Gatelevel simulations. Used in the past ALINT-PRO but this is not free to download. Any suggestions?
-> a free formal verification tool to perform equivalence checking: RTL against gatelevel netlist if functionally equivalent (the gatelevel netlist is just the initial Post Synthesized netlist without SDF). Used in the past LEC (Conformal) from Cadence but this is not free to download. Any suggestions?
07-21-2019 08:38 AM
07-21-2019 09:02 AM
This is the reason why I am asking this question ? Cannot find any at the moment !
There must be at least a free RTL linting tool around ? Anyone else has any suggestions ?
Xilinx Vivado design suite has built-in DRCs (Design Rule Checks) but not linting. Is this the case ?
07-21-2019 03:14 PM
I use Verilator as a free linting tool for Verilog. I've really fallen in love with it as well. Sadly, it doesn't do VHDL. There is a ghdl tool for VHDL, but I don't know how good it is at linting.
As for formal, there is a free formal verification tool known as SymbiYosys, and a companion commercial product known as the SymbioticEDA Suite. While it doesn't do equivalency checking (well), it can handle your basic assertion based formal property verification. The free version is limited to Verilog, with a small subset of SystemVerilog added in--to include support for immediate assertions.
Feel free to check out the ZipCPU blog or even send me a message if you'd like to know more,
07-21-2019 04:01 PM
Whats the reason you need them?
Never used either in 15 years of FPGA development and done just fine. Given the nature of VHDL, you dont get a lot of the stuff you need to lint Verilog for.
Theres a reason ASIC people pay top end prices for such tools.
Sigasi (not free) has VHDL linting
07-22-2019 12:16 AM
I mainly need a formal verification free tool to check RTL-to-Gate if they are functionally equivalent. Tun RTL simulations to my current design and Simulations passed without any BER errors. After I generated the synthesized design (no place and route stage yet was run) and attempted to run Post Synrhesis simulation using the same testbench simulation failed with BER errors. Could look at the simulation in detail to locate where the problem is but if I run formal verification it could report differences. Synthesis may have optimized away a pice if code or an internal signal or reoptimized in a different way one of the IPs. The design I have uses multiple IPs (created few user IPs myself from RTL) and connected these up in a schematic diagram. A linting tool could be useful too to spot any VHDL issues for attention. However, I am aware about all VHDL rules and was careful spotting any obvious issues and correcting them myself.
07-22-2019 12:35 AM - edited 07-22-2019 12:36 AM
Then I think you'll be out of luck, and need to do this like all other FPGA designers.
1. Ensure your testbench is correct. Do any BFMs you have actually follow the specs? Have you really covered all possible cases? are there some corner cases you missed? Is there some untested code because the bit you didnt test was "too obvious to test"?
2. Check through the synthesis logs for any messages about logic removal.
3. Check the RTL and Implementation Schematics. Do they look correct?
4. Put debug registers in the design. Poll them.
5. Use chipscope to do real time debug.
Because its reletively easy to re-compile an FPGA, I doubt my engineers bother with static equivolence checking. Ive also never seen an engineer ever do a post synthesis simulation. Its usually easier to ensure RTL simulation and compilation is correct then go straight to hardware debug. Gate level simulation would only really be for people who are in safety critical applications.
The market for a free static checker would be so small, I dont think I would trust it as I doubt it would have any decent level of support.
Have you followed all the correct design practices for FPGAs?
Full SDC Specs written and design meets timing?
Synth tools are very good nowawdays at creating the circuit that you wrote. So Anything optimised away would likely be a code error, rather than tool issue (they do still happen, but its usually with VHDL 2008). Real synthesis bugs are pretty rare.