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Adventurer
Adventurer
357 Views
Registered: ‎07-29-2013

PL DDR memory tests on ZCU106 fail

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I created an example design with Vivado 2018.3.  I selected Configurable Zynq UltraScale+ MPSoc Design, then choose a default board ZCU106.zynq_ultra_mpsoc_example.png

 

After write_bitstream completed, I created an templates application “memory tests” with SDK. The ZCU106 board have not run properly, even the LED INIT_B was still red.

微信图片_20190725095255.jpg

I created an templates application “Hello World” with SDK, the ZCU106 board printed “Hello World” very well. I used an ila to check the c0_init_calib_complete signal, it was high.

 

Anybody could tell me what’s wrong of this board, or the Vivado have some bug there?

I've found the reason. The psu0_ram could not run  .elf file, so it need placed in the DDR space.

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Mentor watari
Mentor
333 Views
Registered: ‎06-16-2013

Re: PL DDR memory tests on ZCU106 fail

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Hi @wbyjerry 

 

I guess the following URL is helpful for you.

Would you refer it ?

 

AR #71961

https://www.xilinx.com/support/answers/71961.html

 

Best regards,

View solution in original post

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Mentor watari
Mentor
334 Views
Registered: ‎06-16-2013

Re: PL DDR memory tests on ZCU106 fail

Jump to solution

Hi @wbyjerry 

 

I guess the following URL is helpful for you.

Would you refer it ?

 

AR #71961

https://www.xilinx.com/support/answers/71961.html

 

Best regards,

View solution in original post

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