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tomajmich
Visitor
Visitor
6,341 Views
Registered: ‎08-09-2017

PLL: shutdown when Display Port is enabled in the devicetree

Hi,

has anyone come across such message from the kernel? I am wondering what is wrong and what to fix.

The kernel is 17.1 and an excerpt from the boot log is:

.....

[ 1.331953] Write failed gate address:1000f02
[ 1.332068] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[ 1.332195] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[ 1.332320] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[ 1.332443] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[ 1.332566] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[ 1.332683] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[ 1.332805] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[ 1.332925] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[ 1.333008] zynqmp_pm firmware: Power management API v0.3
[ 1.360093] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 1.361881] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 33, base_baud = 6249999) is a xuartps
[ 2.252334] console [ttyPS0] enabled
[ 2.256084] [drm] Initialized
[ 2.259317] [drm] load() is defered & will be called again
[ 2.265547] PLL: shutdown

....

This only happens when I enable DP in my devicetree so this has to do with the clocking of the display port.

I have dp_video_in_clk on the PS driven by a clock wizard, so the dp_sub sections has the xlnx,vid-clk-pl: setting which according to the docs "Should be used when the pixel clock is coming from PL." which is the case.

Any suggestions?

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10 Replies
ibaie
Xilinx Employee
Xilinx Employee
6,053 Views
Registered: ‎10-06-2016

Hi @tomajmich

 

Can you check your vivado design to ensure tha VPLL is used only for clocking the Display Port peripheral?

(Check: TOPSW_MAIN within Advanced clocks...

 

Kind Regards,

Ibai


Ibai
Don’t forget to reply, kudo, and accept as solution.
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ibaie
Xilinx Employee
Xilinx Employee
6,036 Views
Registered: ‎10-06-2016

Hi @tomajmich

 

An official AR#69764 has been released to address this issue, please take a look and provide your feedback.


Ibai
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j_gavillan
Visitor
Visitor
5,966 Views
Registered: ‎05-05-2017

Hi,

 

In my case I get the PLL shutdown on display port after about 10 minutes and after that my monitor loses the image. I know for sure that VPLL is only used for DP_VIDEO.  Is this some kind of sleep mode function ?

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cnovikov
Newbie
Newbie
5,897 Views
Registered: ‎07-18-2017

It looks like Xilinx's console blanking function is buggy and kills the DisplayPort console instead exactly 10 minutes after boot-up.

 

Regarding the "PLL: shutdown" message, it is normal and means that the code is reprogramming the PLL. As long as it is eventually followed by "PLL: enable", it is OK.

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legoman
Observer
Observer
5,881 Views
Registered: ‎06-14-2012

On answer record it says that:

"Note: VPLL should be used only for Display Port (DP_VIDEO)."

 

Which clocks I should use for the DP_AUDIO and DP_STC?

waldemar
Visitor
Visitor
5,394 Views
Registered: ‎10-12-2017

Hi,

 

I'm a novice with these devices and I'm currently running into this error message 

[    3.030222] xilinx-dp-snd-pcm amba:dp_snd_pcm0: Xilinx DisplayPort Sound PCM probed
[    3.037884] xilinx-dp-snd-pcm amba:dp_snd_pcm1: Xilinx DisplayPort Sound PCM probed

I have just ultrascale MPSoC on my vivado design and I'm trying to run Linaro Ubuntu Desktop on it. Where do I make these " set TOPSW_MAIN to DPLL and DP_VIDEO to VPLL." changes?

 

Thanks.

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steven.bell
Contributor
Contributor
5,015 Views
Registered: ‎01-24-2013

I don't think those are errors; "probing" is the term for loading a kernel driver, and this is just indicating that the DP sound drivers have been loaded.

 

That said, you can set the clocks in the customization window for the ZynqMP.  Go to the "Clock configuration" pane, and select the "Output clocks" tab.  TOPSW_MAIN is in the "Advance clocks" section, under "Full power domain".

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4,835 Views
Registered: ‎11-10-2017

Hi,

I realize this is a bit late, but I think you can find the settings you need by re-customizing the processor in the block diagram (probably by double-clicking on it), then selecting "Clock Configuration" on the left.  You should then select "Output Clocks" and expand Advance Clocks..Full Power Domain..Interconnect and Switch clocks to find TOPSW_MAIN.  You can select DPLL from the drop-down list.

 

Jason

 

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panateq65
Newbie
Newbie
4,238 Views
Registered: ‎01-01-2018

Yes I have the same problem also ... Not sure if it is hadrware related or not ...

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steven.bell
Contributor
Contributor
3,162 Views
Registered: ‎01-24-2013

For anyone dealing with this in the future: if you have debugfs enabled in the Linux kernel, you can print out /sys/kernel/debug/clk/clk_summary to get a full description of the clock tree.  I found that I had to do a clean rebuild of Petalinux for it to pick up some changes to my clock configuration.