on the headphone output I can barely hear an extremely high pitch tone on the headphone out.
After reading through the source I realised this project is setup for a 100Mhz clock while my board is 50M. I modified the synth.vhd as below:
entity synth is
port(clk : in std_logic;
syn_out : inout std_logic_vector(7 downto 0));
architecture Behavioral of synth is
signal sclk : std_logic_vector(10 downto 0);
if clk'event and clk = '1' then
-- divide a clock by "10111010101" (1493) which is about the value of 100M/256/261.6
-- where 100M is the clock frequency on a Nexys3
-- 256 is the number of points in the sine wave table
-- 261.6 is the frequency of a middle C
if sclk = "1011101010" then -- MODIFIED decreased by half for 50Mhz clk (746 is new clock divider)
--"11111111" is 255 is the maximum point in the sine wave table
if syn_out < "11111111" then
syn_out <= syn_out + 1;
syn_out <= "00000000";
sclk <= "00000000000";
sclk <= sclk + 1;
And re-programmed however this made absolutely no difference to the faint high pitched tone .
I've tried through speakers incase it was a gain issue, but to no avail. Also adjusting the pot on the PMOD itself.
Just wondering if anyone else has had any experience with this module/board combination?
Unfortunately I don't have access to an oscilliscope so can't see if the intermediate PWN signal is being correctly generated.
I also have the PMOD DA2 but thought I'd start with this as before jumping into the deep(er) end.