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Visitor nahir
Visitor
7,545 Views
Registered: ‎02-05-2014

Pin placement on the VC709 kit

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Hi Folks,

  I'm new to all of this, so sorry for the newbee question (I did search for an answer, but did not find).

 I recently purchased a Virtex -7 FPGA VC709 Connectivity Kit.

 I've successfully set up the Vivado IDE, brought up a project etc., but the bitstream generation fails on pin placement (namely, I haven't defined anything).

  All I have is a piece of VHDL that I want to run, drive a clock into, and see the output (in a way similar to what ChipScope provides).

  Can someone assist?

  - Where can I find the list of pins for this board?

  - How do I define the placement?

 

Thanks!!

  Amir

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1 Solution

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Xilinx Employee
Xilinx Employee
13,062 Views
Registered: ‎07-11-2011

Re: Pin placement on the VC709 kit

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Hi,

 

You can find all the kit related documents here, XTP213 section gives you schematic, XDC.

You can define the placements following UG903

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug903-vivado-using-constraints.pdf

 

Hope this helps

 

Regards,

Vanitha

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2 Replies
Xilinx Employee
Xilinx Employee
13,063 Views
Registered: ‎07-11-2011

Re: Pin placement on the VC709 kit

Jump to solution

Hi,

 

You can find all the kit related documents here, XTP213 section gives you schematic, XDC.

You can define the placements following UG903

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug903-vivado-using-constraints.pdf

 

Hope this helps

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

Xilinx Employee
Xilinx Employee
7,523 Views
Registered: ‎08-02-2007

Re: Pin placement on the VC709 kit

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Hi,

 

The exact pin location that is used on VC709 is available in the Appendix 

 

For XDC refer page 71 of http://www.xilinx.com/support/documentation/boards_and_kits/vc709/ug887-vc709-eval-board-v7-fpga.pdf

 

Thanks,

Hem

 

 

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