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priy1909
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Registered: ‎12-29-2020

Pinout of minized board and its I/O standards

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Hi All,
I am using MiniZed board in MATLAB and using its feature FPGA in Loop. MiniZed board is not listed in the board list so i am trying to use it as custom board. Can anyone help me to fill these entries for MiniZed board ?
FPGA input clock:
1. Clock frequence:
2. Clock Pin number:

3. Clock IO standards :

4. Clock Type (Singe ended or differential)

Reset:

1. Reset Pin number:

2. Reset IO standards :

3. Active level

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@priy1909 You can reference http://www.minized.org/ then select Support > Documentation and scroll down to MiniZed and select View.

Schematic:  http://minized.org/sites/default/files/documentations/MiniZed_Rev_1_Schematic.zip

Getting Started Guide:  http://minized.org/sites/default/files/documentations/MiniZed-GSG-v1_2.pdf

Constraints:  http://minized.org/sites/default/files/documentations/MiniZed_Constraints_Rev1_170613.zip

With all that said, I think this will depend on your configuration of the Zynq-7000 PS.  The MiniZed targets the XC7Z007S-CLG225 which only has 54 SelectIO and none of those 54 pins appear to be bringing in a clock source (on the MRCC/SRCC pins).  This would suggest the PL is dependent on the PS to provide a fabric clock (FCLK_CLK0/1/2/3).

It also does not appear to be a dedicated reset input into the SelectIO.  Therefore, you would need to define your where your reset is coming from.  It looks like signal PL_SW (SW1 driving pin E11 in IO Bank 35) on the schematic is the only input switch into the PL.

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joancab
Mentor
Mentor
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Registered: ‎05-11-2015

All these details should be in the schematic or user manual

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miker
Xilinx Employee
Xilinx Employee
314 Views
Registered: ‎11-30-2007

@priy1909 You can reference http://www.minized.org/ then select Support > Documentation and scroll down to MiniZed and select View.

Schematic:  http://minized.org/sites/default/files/documentations/MiniZed_Rev_1_Schematic.zip

Getting Started Guide:  http://minized.org/sites/default/files/documentations/MiniZed-GSG-v1_2.pdf

Constraints:  http://minized.org/sites/default/files/documentations/MiniZed_Constraints_Rev1_170613.zip

With all that said, I think this will depend on your configuration of the Zynq-7000 PS.  The MiniZed targets the XC7Z007S-CLG225 which only has 54 SelectIO and none of those 54 pins appear to be bringing in a clock source (on the MRCC/SRCC pins).  This would suggest the PL is dependent on the PS to provide a fabric clock (FCLK_CLK0/1/2/3).

It also does not appear to be a dedicated reset input into the SelectIO.  Therefore, you would need to define your where your reset is coming from.  It looks like signal PL_SW (SW1 driving pin E11 in IO Bank 35) on the schematic is the only input switch into the PL.

Please Reply, Kudos, and Accept as Solution.

View solution in original post