03-25-2018 06:30 AM - edited 03-25-2018 06:31 AM
I am trying use Pmod AD1 (ADC) for connecting to VCU118 pmod port, It is not giving an accurate conversion of analog input, the signal keeps changing (please see in the attached image) even when the analog input is constant?
What would be the exact reason for this?
Here I am attaching the schematic diagram and ILA waveform.
The same design I was implemented on the Nexys Spartan 6 board, it is working perfectly. Just I changed the XDC file for connecting to VCU118 (pins from AV16 to AT16) .
Can you please help out in resolving the problem?
03-25-2018 09:37 AM
03-25-2018 10:39 AM - edited 03-25-2018 10:43 AM
Thank you for your reply. Here is my previous discussion https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/Re-How-to-change-Pmod-level-shifter-to-3-3V-on-Virtex-ultra/td-p/840727 I didn't,t get any reply from several days, So I just reposted the same,
Anyway, I am attaching here.
Many thanks for your reply.
03-25-2018 04:06 PM
>What would be the exact reason for this?
There would be several possible reasons. To be able to answer this question precisely, I'd need to review your pinout and input/output delay constraints, the way you're generating a clock, what it is frequency is, the schematic for the devcard you're using, the pinout and datasheet for the ADC on the pmod, how you're framing the incoming serial data, a simulation with a model based on the AD7476A, and other things.
Since this sounds like work one would be compensated for, if you could explain what you've done to troubleshoot this so far, where you obtained the code to create your interface (did you write it, did you simulate it with a model of the ADC based on the datasheet), what you're driving the ADC with, did you verify it is constant with an oscilloscope, etc.
By the way, I'm not seeing the relationship between your input data on D0 and the long run where you're module is output 0 on data1 in the waveform. Consequently, if I were you, I'd start with a Verilog or VHDL model of the ADC based on the datasheet, if Analog devices doesn't have such a model, and assume your RTL (as much as I can assume with the sparse data and time I have) has a bug.
Upload your RTL for pmodad1_test and I'll see if anything pops out at me. Also let me know what your input clock frequency is on the differential clock.
03-25-2018 04:39 PM
Thank you for your reply.
There are no issues with the pmodad1_test RTL code (this code given by the digilent and verified for joystick application http://hamsterworks.co.nz/mediawiki/index.php/PmodAD1).
The clock frequency of my design is 100MHz, Here I am attaching the RTL and XDC files.
Also, same code I have implemented on spartan-6 using pmod AD1 and I was able to see the ADC converted value on the segment display for corresponding input voltage on AD1 for both D0, D1 channels.
Once again many thanks for the reply.
03-25-2018 06:17 PM - edited 04-03-2018 05:50 PM
First, if you use other's code, you own it. You must simulate it the way you wish to use it, especially if you're still learning.
Digilent provides a great service as far as low cost cards and PMODs go, but I have found their code is rarely if ever usable "as is".
Second, and I do not think this is your problem, but you should use named association in your Verilog, not positional association. You did the following in your top level verilgo, which could lead to future errors if somebody rearranges the VHDL ADC interface module port ordering:
pmodad1_test AD1_UUT( clk, ADC_CS, ADC_SCLK, ADC_D0, ADC_D1, led , data1, data2, data1_shift, data2_shift );
Third, the VHDL is using (and this is not your problem) a deprecated/squatter package, and noting in the code requires it:
Fourth, just not the last of the items I've noticed, initializing to 'X' is not meaningful in *synthesis*. It can be helpful when running a testbench, but you should fix that after you're done troubleshooting:
signal ce_sr : std_logic_vector(3 downto 0) := (others=>'X'); signal sequncer_shift_reg : std_logic_vector(18 downto 0) := (others=>'X'); signal clock_state : std_logic := 'X'; signal clock_enable : std_logic := 'X'; signal din0_shift_reg : std_logic_vector(15 downto 0) := (others=>'X'); signal din1_shift_reg : std_logic_vector(15 downto 0) := (others=>'X');
In any event, I have a hunch that if you write a testbench and a model based on the datasheet model (or find and "own", as in understand every line of code and believe it is correct), I suspect you will figure it out. I identified two possible problems very quickly (not mentioned above) after a quick test. You could even download somebody else's testbench and model (but you will have to own it) and compare against what you see in the datasheet.
It looks like you've been working at this for several months. What is your background? Student (undergrad or grad) major? Are you a working engineer with years of experience just not with Verilog / VHDL / FPGAs?
My suggestion is to write a test bench, obtain or write a model of the ADC you're using, read its datasheet in any event to compare to the waveform you see in the testbench, and rewrite your ADC interface module you found online. Try to make the signals your module is driving to the ADC look like what you see in the datasheet. Also verify that your clock is really 100 MHz, and that you've met all electrical and timing requirements to the external ADC.
In closing, it would be nice if you went back and thanked engineers who helped you with the kudos, and accepted solutions you've received. You've received quite a bit of valuable time from many people already. Hopefully someday you will repay the favor.