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ingempo
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Registered: ‎11-10-2011

Problem in ML505 SGMII Design Creation

Hi ! 

 

I have the hope that some persons of Xilinx Community could help me. All help to get it to work is appreciated. 

 

I have followed held up the steps indicated in the tutorial ML505/506 SGMII Design Creation using 10.1.03 CORE Generator: http://www.xilinx.com/products/boards/ml505/docs/ml505_sgmii_design_creation.pdf

 

Nevertheless, when I sending data packets from the command console of Windows, the card does not answer (The Led TX does not light).

 

After restarting the PHY layer, the led DUP (DS33) and LINK100 (DS31) are established.

Via GPIO LED's I can see  that EMAC1CLIENTRXFRAMEDROP='1' without having sent any data. 

Is there any problem with this?

 

I am really frustrated, because I have weeks trying to implement communication via ETHERNET.

 

Card, Software and Hardware Description:

 

Virtex 5 XUPV5-LX110T

Xilinx ISE and Core Generator 10.1.3

USB-JTAG Programming Cable

Windows XP SP2

Wireshark 1.6.2

CAT-5 Crossover Cable

Realtek RTL8139 Family - Fast Ethernet Adapater

  • IP Address: 1.2.3.9 (192.168.1.3 tried too)
  • Subnet Mask: 255.255.255.0 (255.0.0.0 tried too)
  • Net Address: Absentee
  • Size of plugs of reception: 64K bytes
  • Link Speed/Duplex Mode: Auto

Virtex5 Embedded Tri-mode Ethernet MAC Wrapper 1.5

 

Host Type: None

Enable MAC0 (Disable MAC1)

PHY Interface: SGMII

Speed: Tri-Speed

SGMII Capabilities: 10/100/1000 Mb/s (no clock constraints required)

Flow Control Configuration: TX and RX Flow Control Enable

 

Changes in (v5_emac_v1_5_example_design.vhd) file

 

PHY Reset Logic Added and reset_i signal inverted

 

...

-- Asynchronous Reset
RESET : in std_logic;
PHY_RESET_0 : out std_logic-- PHY Reset Logic
);


end v5_emac_v1_5_example_design;

 

...

 

---------------------------------------------------------------------------
-- Reset Input Buffer
---------------------------------------------------------------------------
reset_ibuf : IBUF port map (I => RESET, O => reset_i);
PHY_RESET_0 <= not reset_i;-- Invert the Reset signal (Active Low on ML505)

 

...

    

Changes in (v5_emac_v1_5.vhd) file

 

Change in constant 

 

...

-- PCS/PMA Auto-Negotiation Enable (not enabled)
constant EMAC0_PHYINITAUTONEG_ENABLE : boolean := TRUE;-- Default: TRUE

...

 

Changes in (v5_emac_v1_5_example_design.ucf) file

 

# Place the transceiver components. Please alter to your chosen transceiver.
INST "*GTP_DUAL_1000X_inst?GTP_1000X?tile0_rocketio_wrapper_i?gtp_dual_i" LOC = "GTP_DUAL_X0Y3";
INST "MGTCLK_N" LOC = "P3";
INST "MGTCLK_P" LOC = "P4";

NET "RESET" LOC = U8; # ML505 GPIO North Push Button (SW10)
NET "RESET" PULLUP;

NET "PHY_RESET_0" LOC = J14; # ML505 PHY_RESET

# CLIENT RX INTERFACE

NET "EMAC0CLIENTRXDVLD" LOC = H18; # GPIO LED 0
NET "EMAC0CLIENTRXFRAMEDROP" LOC = L18; # GPIO LED 1

NET "EMAC0CLIENTRXSTATS[6]" LOC = K34; # J4 PIN 2
NET "EMAC0CLIENTRXSTATS[5]" LOC = K32; # J4 PIN 6
NET "EMAC0CLIENTRXSTATS[4]" LOC = N32; # J4 PIN 10
NET "EMAC0CLIENTRXSTATS[3]" LOC = R34; # J4 PIN 14
NET "EMAC0CLIENTRXSTATS[2]" LOC = R32; # J4 PIN 18
NET "EMAC0CLIENTRXSTATS[1]" LOC = T34; # J4 PIN 22
NET "EMAC0CLIENTRXSTATS[0]" LOC = U31; # J4 PIN 26

NET "EMAC0CLIENTRXSTATSVLD" LOC = P32; # J4 PIN 12
NET "EMAC0CLIENTRXSTATSBYTEVLD" LOC = T33; # J4 PIN 16

# CLIENT TX INTERFACE

NET "CLIENTEMAC0TXIFGDELAY[7]" LOC = V33; # J4 PIN 30
NET "CLIENTEMAC0TXIFGDELAY[6]" LOC = V34; # J4 PIN 34
NET "CLIENTEMAC0TXIFGDELAY[5]" LOC = AA33; # J4 PIN 38
NET "CLIENTEMAC0TXIFGDELAY[4]" LOC = AE34; # J4 PIN 42
NET "CLIENTEMAC0TXIFGDELAY[3]" LOC = AE33; # J4 PIN 46
NET "CLIENTEMAC0TXIFGDELAY[2]" LOC = AD34; # J4 PIN 50
NET "CLIENTEMAC0TXIFGDELAY[1]" LOC = AB32; # J4 PIN 54
NET "CLIENTEMAC0TXIFGDELAY[0]" LOC = AB33; # J4 PIN 58
NET "CLIENTEMAC0TXIFGDELAY*" PULLDOWN; # PORT PULLDOWN

NET "EMAC0CLIENTTXSTATS" LOC = R33; # J4 PIN 20
NET "EMAC0CLIENTTXSTATSVLD" LOC = U33; # J4 PIN 24
NET "EMAC0CLIENTTXSTATSBYTEVLD" LOC = U32; # J4 PIN 28

# MAC CONTROL INTERFACE

NET "CLIENTEMAC0PAUSEREQ" LOC = V32; # J4 PIN 32
NET "CLIENTEMAC0PAUSEREQ" PULLDOWN; # PORT PULLDOWN

NET "CLIENTEMAC0PAUSEVAL[15]" LOC = H33; # J6 PIN 2
NET "CLIENTEMAC0PAUSEVAL[14]" LOC = F34; # J6 PIN 4
NET "CLIENTEMAC0PAUSEVAL[13]" LOC = H34; # J6 PIN 6
NET "CLIENTEMAC0PAUSEVAL[12]" LOC = G33; # J6 PIN 8
NET "CLIENTEMAC0PAUSEVAL[11]" LOC = G32; # J6 PIN 10
NET "CLIENTEMAC0PAUSEVAL[10]" LOC = H32; # J6 PIN 12
NET "CLIENTEMAC0PAUSEVAL[9]" LOC = J32; # J6 PIN 14
NET "CLIENTEMAC0PAUSEVAL[8]" LOC = J34; # J6 PIN 16
NET "CLIENTEMAC0PAUSEVAL[7]" LOC = L33; # J6 PIN 18
NET "CLIENTEMAC0PAUSEVAL[6]" LOC = M32; # J6 PIN 20
NET "CLIENTEMAC0PAUSEVAL[5]" LOC = P34; # J6 PIN 22
NET "CLIENTEMAC0PAUSEVAL[4]" LOC = N34; # J6 PIN 24
NET "CLIENTEMAC0PAUSEVAL[3]" LOC = AA34; # J6 PIN 26
NET "CLIENTEMAC0PAUSEVAL[2]" LOC = AD32; # J6 PIN 28
NET "CLIENTEMAC0PAUSEVAL[1]" LOC = Y34; # J6 PIN 30
NET "CLIENTEMAC0PAUSEVAL[0]" LOC = Y32; # J6 PIN 32
NET "CLIENTEMAC0PAUSEVAL*" PULLDOWN; # PORT PULLDOWN

# EMAC-MGT LINK STATUS

NET "EMAC0CLIENTSYNCACQSTATUS" LOC = W32; # J6 PIN 34
NET "EMAC0ANINTERRUPT" LOC = AH34; # J6 PIN 36

# SGMII INTERFACE

NET "PHYAD_0[4]" LOC = AH32 | PULLDOWN; # J6 PIN 42
NET "PHYAD_0[3]" LOC = AK34 | PULLDOWN; # J6 PIN 44
NET "PHYAD_0[2]" LOC = AK33 | PULLDOWN; # J6 PIN 46
NET "PHYAD_0[1]" LOC = AJ32 | PULLUP; # J6 PIN 48
NET "PHYAD_0[0]" LOC = AK32 | PULLDOWN; # J6 PIN 50

### need AR??
INST *?v5_emac EMAC0_PHYINITAUTONEG_ENABLE = TRUE;

 

Command Window

 

arp -s 1.2.3.5 00-18-3e-00-db-eb

ping -w 1 -n 1 1.2.3.5

 

Thanks Very Much !

 

Attachment: Wireshark Image 

--
Esteban
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ingempo
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Registered: ‎11-10-2011

I have forgotten to define the constraints of TX and RX of the interface SGMII in the file (v5_emac_v1_5_example_design.ucf):

 

NET "TXP_0" LOC = M2; # SGMII TX P
NET "TXN_0" LOC = N2; # SGMII TX N
NET "RXP_0" LOC = N1; # SGMII RX P
NET "RXN_0" LOC = P1; # SGMII RX N

 

When synthesize, some errors this are at sight. Searching I thought that it is necessary to to change

 

INST "*GTX_DUAL_1000X_inst?GTX_1000X?tile0_rocketio_wrapper_gtx_i?gtx_dual_i" LOC = "GTX_DUAL_X0Y4";

 

Why? In the schematics of ML505  shows that is LOC=X0Y3 (Bank 112) who driven the interface SGMII.

 

I have done these changes, but even it does not work.

 

 

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Esteban
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mcgett
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Registered: ‎01-03-2008

> Why? In the schematics of ML505  shows that is LOC=X0Y3 (Bank 112) who driven the interface SGMII.

 

In your original post you said that you were using the "Virtex 5 XUPV5-LX110T".  This is not a ML505 board, but a similar board (same PCB) but a different device which has different placement constraint requirements.

 

 

------Have you tried typing your question into Google? If not you should before posting.
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ingempo
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Registered: ‎11-10-2011

Thanks for your reply mcgett !

 

Finally the placement constraint for the GTP DUAL is:

 

INST "*GTP_DUAL_1000X_inst?GTP_1000X?tile0_rocketio_wrapper_i?gtp_dual_i" LOC = "GTP_DUAL_X0Y4";
INST "MGTCLK_N" LOC = "P3";
INST "MGTCLK_P" LOC = "P4";

 

Nevertheless even it does not work.

 

 

 

 

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Esteban
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ingempo
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Registered: ‎11-10-2011

Via GPIO LED's I can see also that the output state of the GTP is:

 

EMAC0CLIENTSYNCACQSTATUS = 1

 

This wants to say that the trasmisor works correctly.

 

Nevertheless even it does not work.

Some Suggestion?

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Esteban
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jijisirine
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Registered: ‎10-29-2011

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