cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
1,110 Views
Registered: ‎12-13-2017

Problem with Independent JTAG mode

Hello,

 

I'm working with Zedboard and I'm trying to enable the Indipendent JTAG for debbugging PS and PL separately.

 

So, I set the MIO2 jumper to 3.3V and set the boot from JTAG. Then, I loaded an .bit file that switches the EMIO PJTAG to connector JC1. Finally, I've tried to load an hello_word application using Xilinx Platform Cable connected to JC1 but the SDK report an error on JTAG connection.

 

Can anyone help me?

 

Thanks

0 Kudos
4 Replies
Moderator
Moderator
1,064 Views
Registered: ‎11-09-2015

Re: Problem with Independent JTAG mode

Hi @raffaele_fantauzzi,

 

Please check the AR#47599, it seems to describe your issue.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
1,059 Views
Registered: ‎12-13-2017

Re: Problem with Independent JTAG mode

Thanks,

 

I've already read this document.

So, I've decided to start the same procedure using a Zynq Industrial on my custom board (therefore not CES device), but the problem is not solved.

 

Can you help me?

 

Thanks

 

 

0 Kudos
Highlighted
Moderator
Moderator
1,056 Views
Registered: ‎11-09-2015

Re: Problem with Independent JTAG mode

Hi @raffaele_fantauzzi,

 

Did you check this topic:

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/How-to-program-PL-and-use-of-JTAG-ports/td-p/551383

 

It says that you need to source ps7_init.tcl before loading the bitstream to have the PS in a known state. Did you do it?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
1,049 Views
Registered: ‎12-13-2017

Re: Problem with Independent JTAG mode

Hi,

 

the steps I've done are:

 

1) start-up the board with mio2 at high level (independent JTAG mode) end boot from JTAG

2) load a .bit file on PL JTAG that routes connection between PJTAG-EMIO on I/O pins

3) try to load an application in debug mode with SDK using PJTAG-EMIO connection, but without any success

 

The discussion you suggested me talks about "then program the muxing in FSBL and AFTER that you can use the PJTAG separatly", but the FSBL is referred of boot from FLASH and on UG585 I remember is wrote that the boot has to set from JTAG. Sorry, I don't understand.

 

Moreover, I'm trying to connect to PS through PJTAG on EMIO using tha Platform Cable USB II. It is correct?

 

Thanks a lot

 

 

 

0 Kudos