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Visitor akashkumar
Registered: ‎02-07-2010

Problem with Partial Reconfiguration using AXI-Stream in Zynq UltraScale+ (ZCU102)

I am working with Zynq UltraScale+ ZCU102 Evaluation Board (xczu9eg-ffvb1156-2-e).  I am using Vivado 2018.3. 

I prepared simple partial reconfiguration (PR) design, whereas inside pblock region the custom made Adder and Subtractor IP resides, so that during run time we can choose which arithmetic instruction we want to perform for a particular data set. In this case, AXI-Lite (GP) ports are used for data communication. This design perfectly works on Zynq UltraScale+ ZCU102 .

Later, I changed AXI-Lite (GP) port to AXI-stream (HP) port in the same PR design, but in this case the design don't work at all. It always get stuck.

In addition,  I am loading the partial bitstream (*.bit file) through vivado.

Can any one help me on this regards? Why the partial reconfiguration mechanism is not working for AXI-stream ports on  Zynq UltraScale+ ZCU102?

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