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rodolfogomes
Adventurer
Adventurer
3,135 Views
Registered: ‎10-01-2014

Problem with hardware ethernet co-simulation using VC707

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Dear all,

 

First of all, many thanks in advance.

 

I come across for the first time with the HW system generator co-simulation using a point-to-point Ethernet connection. As tutorial example, I have followed the following one: https://www.xilinx.com/video/hardware/hardware-co-simulation-vivado-system-generator-for-dsp.html and developed my own HW design as follows:

 

Capture.PNG

 

However, when I run the simulation the FPGA fan stops for a while, and in a few seconds later it starts working again, which might cause some temperature issues!.

 

The only thing I haven't defined was the clock pin location in the clocking tab of the Xilinx token. Could this be causing this? I am really concerned about this because I do not want to burn out the FPGA chip... If yes, should I defined the clock pin ports of my Virtex7 like this:

 

Capture2.PNG

 

Looking forward to hearing from you,

 

Rodolfo

 

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umamahe
Xilinx Employee
Xilinx Employee
3,577 Views
Registered: ‎08-01-2012

Not only temperature issue but it also it could be timing issue.

 

Which version Xilinx tools are you using? 

 

Also verify VC707  debug checklist steps below to make sure the board is fine. 

 

https://www.xilinx.com/support/answers/51233.html

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umamahe
Xilinx Employee
Xilinx Employee
3,578 Views
Registered: ‎08-01-2012

Not only temperature issue but it also it could be timing issue.

 

Which version Xilinx tools are you using? 

 

Also verify VC707  debug checklist steps below to make sure the board is fine. 

 

https://www.xilinx.com/support/answers/51233.html

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

View solution in original post

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