Problem with hardware ethernet co-simulation using VC707

[rodolfogomes]

Dear all,

First of all, many thanks in advance.

I come across for the first time with the HW system generator co-simulation using a point-to-point Ethernet connection. As tutorial example, I have followed the following one: https://www.xilinx.com/video/hardware/hardware-co-simulation-vivado-system-generator-for-dsp.html and developed my own HW design as follows:

However, when I run the simulation the FPGA fan stops for a while, and in a few seconds later it starts working again, which might cause some temperature issues!.

The only thing I haven't defined was the clock pin location in the clocking tab of the Xilinx token. Could this be causing this? I am really concerned about this because I do not want to burn out the FPGA chip... If yes, should I defined the clock pin ports of my Virtex7 like this:

Looking forward to hearing from you,

Rodolfo

[umamahe · Accepted solution]

Not only temperature issue but it also it could be timing issue.

Which version Xilinx tools are you using? 

Also verify VC707  debug checklist steps below to make sure the board is fine. 

https://www.xilinx.com/support/answers/51233.html