I have a working Vivado 2015.1 block design using AXI interconnect with Microblace and some peripherals.
Next, I want to add the AXI QUAD SPI 3.2 core to make the SPI Flash of the AC701 board accessible by the MB.
1. There are some configuration options like XIP mode and Performance mode. Do I have to check them?
2. Is there a QSPI Flash example using Vivado block design? All I found so far is an example for the Virtex-5 with ISE.