06-15-2013 10:47 PM
I'm using a Xilinx PROM as data memory and need to know how is it possible to read and write with a custom hardware? If yes let me know how is its sequence and timing specification through JTAG port?
10-29-2013 02:33 PM
Hi everybody again,
'm using a Xilinx PROM as data memory and previously posted a message in forum about jtag interface. Now I have my own implementation of jtag interface hardware and could write data into PROM flash memory. After writing with custom hardware, I read the content back to a file by xilinx ise and saw the written data in it. I do all steps according to xilinx bsd files for XCF02S flash memory. But, when I'm tring to read it via jtag interface, with address shift command and address shift and appling read command waiting 50us needed. Then I start to read out by shifting out the data, but the captured data is not the written one. Let me know what is wrong with my jtag hardware and read sequence?
Thanks a lot,
10-29-2013 09:48 PM
Firstly there is a user guide for the Platform Flash for Xilinx. Please check Pg 78 onwards of the Xilnx platform flash user guide for the 3rd party programmer guidelines - http://www.xilinx.com/support/documentation/user_guides/ug161.pdf. Make sure you are following all these guidelines while programming.
Instead of manually reading back, you can click on the device and do "Verify", which will automatically verify the flash programmed image for your. Check and let me know the output.
However i guess you are using this flash for programming the FPGA. Did you try programming the FPGA with this. If yes, what is the output.
Send me all the console logs and the bsd and other files so that i can check and let you know if there is something which is missing.
10-30-2013 01:37 AM
Thanks for your reply.
As I said in my post, I am using this flash as data memory too and write and read sequece depends on dynamic treatment of the system. Firstly I want to verify the write and read process to be sure in application everything will work fine. I could do the write process successfully and checked the written data in memory by xilinx impact. But, when I want to read the expected data and put it on test LEDs or send it to the PC via a serial port in application, the captured data is not the same with written one. Let me check my read sequence with ug161 xilinx document. Hope to resolve the problem as soon as possible.
10-30-2013 01:08 PM
I checked that user guide and some other documents from references of original document, but I can't find any solution for my problem. Let me make it more clear, imagine you are using fpga to design a system which you can change the program stream for fpga dynamically or store some application data inside the same memory. So you need to implement your own hardware for jtag interface if you want to use a PROM flash memory (xcf02s). Now you implemented your hardware based on jtag standard state machine and xilinx bsd file (expected read and write flow via jtag interface). Based on defined write flow (attached the bsd file) the write flow was done and I checked the content of the PROM using ISE and programmer platform. But for reading the stored data from fpga using custom hardware we have a problem. Based on flow below (from bsd file) we should first apply address shift command and then send the 16-bit address to address register, after 1 cycle of TCK we need to apply read command and wait 50us. Finally it is time to read out the data (4096 bits with crc). I stored the 32-bit data in lsb side of 4096 bit block in memory, but there is no valid data available in almost 200 bits from lsb side of captured 4096 bits. Also I can't find the size of CRC field. Let me know what is wrong with my sequence and how can I resolve this problem as soon as possible.
"flow_read(array) " &
"INITIALIZE " &
"(ISC_ADDRESS_SHIFT 16:$addr=0 wait TCK 1)" &
"(ISC_READ wait 50.0e-6 4096:!:CRC)" &
"REPEAT 511 " &
"(ISC_ADDRESS_SHIFT 16:$addr+32 wait TCK 1)" &
"(ISC_READ wait 50.0e-6 4096:!:CRC)," &