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Adventurer
Adventurer
3,753 Views
Registered: ‎04-09-2010

Reg TEMAC on sp605 board

Hi all,

 

I want to use TEMAC provided on sp605 board in simple echo mode using edk tool. Was getting confused with what 'reference clock' to select and what 'processor clock' to use? As user clock provided on board is 27Mhz, which i find is very less for a gig ethernet usage/

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3 Replies
Xilinx Employee
Xilinx Employee
3,743 Views
Registered: ‎01-03-2008

Re: Reg TEMAC on sp605 board

There are other clocks on the SP605 that should be used and this are documented in the SP605 Hardware User Guide, UG526.

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Visitor sheac12
Visitor
3,706 Views
Registered: ‎03-08-2010

Re: Reg TEMAC on sp605 board

The Xilinx rep is correct and not. There is only one native clock on the board(SP605) you can use for the generation of the RX/TX clock. There are SMA connectors that could be fed with an external ref, but this requires more test equipment.

 

The onboard clock is  the 200MHz clock, known in the ucf as the SYSCLK. You will need to bring in the differential clock through a IBUGFS, which is then routed to a BUFIO2, which is then feed into a DCM. You can use DCM(SP) to divide the clock down, by setting the CLKFX_DIVIDE = 8 and CLKFX_MULTIPLY = 5.

 

CLKFX_DIVIDE          => 8,
    CLKFX_MULTIPLY    CLKFX_DIVIDE          => 8,  and  CLKFX_MULTIPLY        => 5, generating a 125MHz at the FX output.

 

 

If you want I can provide you with a working example. I, personally, think Xilinx needs to step up with their examples for this board and provide more compilable and working examples of EACH of the boards parts. Not references that depend on XPS.

 

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Newbie jvanderpool
Newbie
3,602 Views
Registered: ‎08-31-2010

Re: Reg TEMAC on sp605 board

Does the clock not feed in from the PHY 88E1111.  I see it accepts a 25MHz crystal and I though that signal was PLL'ed then sent to the FPGA.  I am also trying to create a loop back with the design example provided by the TEMAC core but unsuccessful thus-far.  

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