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ken2ken
Newbie
Newbie
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Registered: ‎12-12-2009

Regarding the SPI between ADC and DE2 board

This is interface between ADC and FPGA and it is held inside FPGA controller. There is no syntax error but it give me no output in the waveform for the stimulation. Can anyone please help me figure it. Thanks.

 

bassman59  , thanks for your reply. I tried to change to the type of data you have mentioned but it seen like lot of syntax errors occurs especially after i replaced the arith and unsigned to numeric_std.

 

Code:

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
LIBRARY work;

ENTITY ADS IS
PORT ( CLK, Data_in, Input_convst, modeselect_A0 : IN STD_LOGIC;
       SCK, ADC_convst : OUT STD_LOGIC;
       ADC_PAL_DATA : OUT STD_LOGIC_VECTOR(11 downto 0)
     );
END ADS;

ARCHITECTURE main OF ADS IS
signal parallel : STD_LOGIC;
signal data_register : STD_LOGIC_VECTOR(11 downto 0);
signal counter1,counter2,counter3,counter4 : STD_LOGIC_VECTOR(5 downto 0);
shared variable temp1,temp2,temp3,temp4,syn : STD_LOGIC;

BEGIN

PROCESS(CLK)    -- start conversion
BEGIN
if Input_convst='1' and temp1='0' then
temp1:='1';
temp2:='0';
ADC_convst<='1';
elsif (rising_edge(CLK))then
    if temp1='1' then
        if counter1<000010 then
           counter1<=counter1 + 1;
        elsif counter1 < 001111 then
              if (rising_edge(CLK)) and modeselect_A0='1'then
                  if counter2<"000010" then
                     counter2<=counter2 + 1;
                  end if;
              ADC_convst<='0';
              temp2:='1';
              end if; 
                 
         end if;
    end if;
if temp3='1' then
temp1:='0';
temp2:='0';
counter1<="000000";
end if;
end if;
END PROCESS;


PROCESS(CLK)  -- CLK FOR ADS
BEGIN

if temp2 ='1' and rising_edge(CLK) then
    if counter3<"101000" then
       if counter3="000000" then syn:='1';
       end if;
     counter3<=counter3 + 1;
     syn:=syn xor '1';
     temp3:='0';
    else
      temp3:='1';
      counter3<="000000";
    end if;
end if;
SCK<=syn;
END PROCESS;

parallel<= syn;
         
PROCESS(parallel)   ---  Serial to parallel conversion
BEGIN
if modeselect_A0='1' then
   counter4<="000000";
   data_register<=(others=>'0');
elsif rising_edge(parallel) and counter4<"001111" then
   counter4<=counter4 + 1;
   if (counter4>"000010") then
       data_register(11 downto 1)<= data_register(10 downto 0);
       data_register(0)<= Data_in;
   end if;
end if;
END PROCESS;

ADC_PAL_DATA<=data_register;
       
END main;
         

 

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