02-28-2018 02:09 AM
I have a zc706 FPGA board. Currently I am booting this board (with Linux) from an SD card, and then connecting to it via ethernet cable. This has been working well.
I recently made some changes to the PL, and wanted to add these to the FPGA board. So, I replaced the top.bit file on the SD card with a new top.bit file that I generated in vivado.
Now when I boot the FPGA board, I can no longer connect to it via ethernet. The initialization lights are all the same as previous; the light labeled 'DONE' turns green.
If I connect to the FPGA board using PuTTY, I can see that the boot sequence always stalls on the line:
"xilinx emaclite 40e00000.ethernet: Device Tree Probing"
whereas it doesn't stall there with the working top.bit file.
How do I load the new bit file? Do I need to change the devicetree.dtb or devicetree_vivado.dtb files? Or maybe make a new BOOT.bin? Any help is appreciated.
03-01-2018 04:55 AM - edited 03-01-2018 04:56 AM
did you remove specific things in Hardware that were previously described & required by your devicetree (system description)?
first of all, I am not sure whether 0x40E0000 is located within the PL or PS side of the zynq soc, but it looks like PL to me. In our system the ethernet controller for PS side is located at 0xE000B000.
if you specified a PL based ethernet controller (is that Xilinx Emac?) in your devicetree, but removed the controller from HW & so, removed the address, the system is probably trying to mount a driver then tries to address some registers in that location, but they no longer exist
03-01-2018 11:55 PM
Thank you for the response, Guillaume.
You are partly right - I checked the device tree, and there was an extra ethernet connection specified in the PL which caused the booter to stall at that location.
However, I removed that ethernet connection from the device tree, it still fails to boot. Now it is stalling at the lines:
" i2c /dev entries driver
cdns-i2c e0005000.i2c: 400 kHz mmio e0005000 irq 143 "
So, there seems to be a deeper problem.
I've attached a .txt file showing the booter readout. Are there any other issues that could cause the stall? Could it be a problem with the PL itself?
03-05-2018 02:18 AM
03-07-2018 12:33 AM - edited 03-07-2018 12:43 AM
1. I generated the bitfile using the vivado 'generate bitsream ' function.
2. I retrieved the bitfile as stored in the project folder (/impl_1)
3. I plugged the SD card into my computer, and replaced the old 'top.bit' file on the SD card with the new 'top.bit' file. There are many other files on the SD card, such as a 'boot.bif' file, but I didnt touch those.
4. I re-inserted the SD card to the FPGA, and attempted to boot, resulting in the error messages above.
I never generated a new .bif file.
I have recently tried to re-image the SD card with a new device tree and .hf file, but found the same problems. There definitely seems to be a problem with the bitfile. My project uses zynq_sys IP -- could something have been changed there that would cause this?