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Registered: ‎09-28-2018

SATA device Phy Layer - Artix7

Hi all,

I am using Artix-7 Evaluation board as SATA Device . Vivado version is 2016.2.

Ideal working case: rx_std_signaldetect_i (RX_ELECTRIC_IDLE) should go low after the completion of the OOB Sequence. After rx_std_signaldetect_i (RX_ELECTRIC_IDLE) deasserted, rx_disparity_err(rxdisperr_out) should be zero.

But in our case Disparity error is still there.

A ILA file is been attached for the reference which has  rx_disparity_err(rxdisperr_out).

Also Attached a PDF of the 7series Transceiver configuration made for this design.

And the same 7- Series Trasceiver configuration using for the Atrix-7 as SATA Host and it is woring fine.

Please let us know if there is any changes to be made to meet the requirement. 



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