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Participant
Participant
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Registered: ‎09-11-2010

SP605 Clocking issue

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Clocking does not seem to be working on my project on the SP605 development board.  The clocking is setup with the following statements which I pieced together from the documentation and examples.  I would appreciate any help in determining the problem.

 

 wire    osc_clk_ibufg;
 wire    CLKFBOUT_to_CLKFBIN;
 wire    CLK_Bufg_in;
 wire    CLKM_Bufg_in;
 wire    ECLK_Bufg_in;
 (* clock_signal = "yes" *) wire CLK;
 (* clock_signal = "yes" *) wire CLKM;
 (* clock_signal = "yes" *) wire ECLK;
 
 
BUFG CLK_Buf (
 .O(CLK),
 .I(CLK_Bufg_in));
BUFG CLKM_Buf (
 .O(CLKM),
 .I(CLKM_Bufg_in));
BUFG ECLK_Buf (
 .O(ECLK),
 .I(ECLK_Bufg_in));
 
 
 /* System Clock */
// IBUFG the raw clock input

IBUFGDS #(
  .DIFF_TERM("FALSE"),    // Differential Termination (Virtex-4/5, Spartan-3E/3A)
  .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
                          //   the buffer, "0"-"16" (Spartan-3E/3A only)
  .IOSTANDARD("LVDS_25")  // Specify the input I/O standard
) inibufg (
  .O(osc_clk_ibufg),  // Clock buffer output
  .I(SYSCLK_P),  // Diff_p clock buffer input (connect directly to top-level port)
  .IB(SYSCLK_N) // Diff_n clock buffer input (connect directly to top-level port)
);

 
PLL_BASE #(
 .CLKFBOUT_MULT(2),
 .CLKIN_PERIOD(5.0),
 .CLKOUT0_DIVIDE(16),
 .CLKOUT0_DUTY_CYCLE(0.5),
 .CLKOUT0_PHASE(0.0),
 .CLKOUT1_DIVIDE(8),
 .CLKOUT1_DUTY_CYCLE(0.5),
 .CLKOUT1_PHASE(0.0),
 .CLKOUT2_DIVIDE(16),
 .CLKOUT2_DUTY_CYCLE(0.5),
 .CLKOUT2_PHASE(180.0)
 ) Project_CLKS (
  .CLKFBOUT(CLKFBOUT_to_CLKFBIN),
    .CLKOUT0(CLK_Bufg_in),   // 25Mhz 0 Phase
    .CLKOUT1(CLKM_Bufg_in),  // 50Mhz 0 Phase
    .CLKOUT2(ECLK_Bufg_in),   // 25Mhz 180 Phase
  .CLKFBIN(CLKFBOUT_to_CLKFBIN),
    .CLKIN(osc_clk_ibufg)
    );

 

 

-----------UCF -----------------

 

NET "SYSCLK_P" TNM_NET = "SYSCLK_P";
TIMESPEC "TS_SYSCLK_P" = PERIOD "SYSCLK_P"  5  ns HIGH 50 %;
#
NET "CLK" TNM_NET = CLK;
TIMESPEC TS_CLK = PERIOD "CLK" 40 ns HIGH 50% INPUT_JITTER 2 ps;
NET "CLKM" TNM_NET = CLKM;
TIMESPEC TS_CLKM = PERIOD "CLKM" 20 ns HIGH 50% INPUT_JITTER 2 ps;
NET "ECLK" TNM_NET = ECLK;
TIMESPEC TS_ECLK = PERIOD "ECLK" 40 ns HIGH 50% INPUT_JITTER 2 ps;
##------- Pin Constraints -------
## Clock inputs
NET "SYSCLK_P" LOC = "K21" |IOSTANDARD=LVDS_25;
NET "SYSCLK_N" LOC = "K22" |IOSTANDARD=LVDS_25;
NET "GPIO_LED"      LOC = "D17" |SLEW=SLOW |IOSTANDARD=LVCMOS25;
NET "GPIO_LED_Ready"     LOC = "AB4" |SLEW=SLOW |IOSTANDARD=LVCMOS25;
NET "GPIO_LED_Level<0>"     LOC = "D21"  |SLEW=SLOW |IOSTANDARD=LVCMOS25;
NET "GPIO_LED_Level<1>"     LOC = "W15"  |SLEW=SLOW |IOSTANDARD=LVCMOS25;
NET "GPIO_LED_Level<2>"     LOC = "V19"  |SLEW=SLOW |IOSTANDARD=LVCMOS25;

 

NET "GPIO_Start"  LOC = "G6"  |SLEW=SLOW |IOSTANDARD=LVCMOS15;  # GPIO_BUTTON0

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Participant
Participant
7,412 Views
Registered: ‎09-11-2010

Thanks for your help.  I made sure that all of the parameters, inputs and outputs were defined for the PLL_BASE and I am now getting a clock signel.  I have a lot of debugging to do to ensure that the design is actually working but at least have something to work with.

 

Thanks again

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

You neglected say what the "issue" is.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Instructor
Instructor
8,360 Views
Registered: ‎07-21-2009

You neglected say what the "issue" is.

I keep telling my wife that I can't read minds, but she doesn't believe me.

 

- Bob Elkind

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

@eteam00 wrote:

You neglected say what the "issue" is.

I keep telling my wife that I can't read minds, but she doesn't believe me.


Bob,

Maybe that's because she can read minds too. Game over, my friend... ;)

 

bt

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Instructor
Instructor
8,340 Views
Registered: ‎07-21-2009

@timpe wrote:

@eteam00 wrote:

You neglected say what the "issue" is.

I keep telling my wife that I can't read minds, but she doesn't believe me.


Bob,

Maybe that's because she can read minds too. Game over, my friend... ;)

 

bt


I'll ask my wife what the clocking issue is.

 

- Bob Elkind

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

You should also ask her what version of the tools is being used (e.g. 12.3) and what silicon (ES vs PS) is populated on the board. And if the problem is something observed during the build of the project (e.g. par error) or actual hardware testing. And associated applicable details.

 

bt

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Instructor
Instructor
8,329 Views
Registered: ‎07-21-2009

@timpe wrote:

You should also ask her what version of the tools is being used (e.g. 12.3) and what silicon (ES vs PS) is populated on the board. And if the problem is something observed during the build of the project (e.g. par error) or actual hardware testing. And associated applicable details.

 

bt


She undoubtedly knows all that, and more.

 

- Bob Elkind

SIGNATURE:
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Summary:
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2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

and the fact that I almost posted something different in response here but didn't in the hope that she won't now be mad at me too.

 

#include <treefall_emptyforest.h>

 

 

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Instructor
Instructor
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Registered: ‎07-21-2009

@timpe wrote:

#include <treefall_emptyforest.h>


My wife says:  Douglas Fir, 43 ft tall, 28" circumference, 16 years old, and there were 3 raccoons and a grey squirrel watching.

 

- Bob Elkind

SIGNATURE:
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Summary:
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Mentor
Mentor
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Registered: ‎11-29-2007

 


and there were 3 raccoons and a grey squirrel watching.

Leave them to me... [queue ominous music]

 



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
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Instructor
Instructor
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Registered: ‎07-21-2009

@awillen wrote:

and there were 3 raccoons and a grey squirrel watching.

Leave them to me... [queue ominous music]


Clark:  Where is Eddie? He usually eats these g*ddam things.

Catherine:  Not recently, Clark. He read that squirrels were high in cholesterol.

reference

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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Participant
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Registered: ‎09-11-2010

Sorry for not providing the needed information. 

 

First I am using 11.5 of the software.  This issue I am seeing is no clock when the design is downloaded to the board.

 

Chipscope is not returning any data and is indicating that there is a slow or no clock available.

 

I also have a very simple piece of code that toggles a LED when a push button is pressed.  When the always was based on the push button the LED toggled when I changed it to utilize a clock edge the LED stays on continuously.

 

I have Googled but have not hit upon a combination that helps.

 

Thanks

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Instructor
Instructor
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Registered: ‎07-21-2009

As you may have noticed, tloesch, we've been having some fun while you've been away.

 

Does the FPGA configure?  Does DONE output signal go HIGH?

 

If yes, does *anything* work?  Is there combinatorial logic you can test to prove that the FPGA is operating (even though the clock isn't running) ?

 

Are there any warnings or errors in the Synth or Map detailed reports?  Are all the IO pins present and accounted for in the post-map pin report?

 

- Bob Elkind

SIGNATURE:
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Summary:
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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

> This issue I am seeing is no clock when the design is downloaded to the board.

 

Did you check the Pinout Report file to confirm that the clock was placed in locations K21/K22?

 

> when I changed it to utilize a clock edge the LED stays on continuously.

 

If the LED is toggling on every clock edge it will be too quick for the human eye to register and at 200 MHz it is likely too quick for the LED to respond.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Participant
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Registered: ‎09-11-2010

>Does the FPGA configure?  Does DONE output signal go HIGH?

 

Yes, the configuration goes fine and the done LED lights.

 

>If yes, does *anything* work?  Is there combinatorial logic you can test to prove that the FPGA is operating (even though the clock isn't running)

 

Almost all of the design is procedural;  The reset logic below which reset the design and turned on an LEN when a button was pressed worked: 

 

assign GPIO_LED_Ready = ~SearchNow;

always@(GPIO_Start) begin

if (GPIO_Start == `True)

SearchNow <= `False;

else SearchNow <= `True;

 

end

 

The code would turn on the LED when the button was pressed and turn it off when the button was let go.

 

assign GPIO_LED_Ready = ~SearchNow;
 always@(posedge CLK) begin
  if (GPIO_Start == `True)
   SearchNow <= `False;
   
    else SearchNow <= `True;
   
  end

 

With this code the LED is always on.

 

I confirmed that the pinouts are placed in K21/K22.

 

There are a number of info and warnings in the synth and Map reports.  The message below from the Map report is referencing the clock.  I looked up Compensation variable and did not find INTERNAL as an option for System_synchronous:

 

MapLib:841 - Changing COMPENSATION attribute from SYSTEM_SYNCHRONOUS to INTERNAL for PLL_ADV Project_CLKS/PLL_ADV.

 

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Instructor
Instructor
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Registered: ‎07-21-2009

Can you verify that CLK is actually a working clock signal?

  • Is the CLK signal used anywhere else in the design?
  • Have you checked the source clock input signal to the FPGA?

You should post the clock signal path from input to PLL to distribution buffer.  The MAP warning message suggests a problem with the PLL instantiation.  Did you copy the code for the PLL from the SP605 board baseline design, or is this a change from the baseline code?

 

I'm not a Verilog language authority, but I'm completely unfamiliar with the syntax 'TRUE   (with the prepended apostrophe).

Example:  if (GPIO_Start == `True)

 

These are examples of syntax in which I'm confident::

if (GPIO_Start == 1)

if (GPIO_Start )

 

Finally, the code you wrote as follows

 

assign GPIO_LED_Ready = ~SearchNow;

always@(GPIO_Start) begin
  if (GPIO_Start == `True)
    SearchNow <= `False;
  else SearchNow <= `True;
end

 

 

Can be replaced with:

 

assign GPIO_LED_Ready = GPIO_Start;

Clocked version:

 

reg GPIO_StartQ;
always @(posedge CLK) GPIO_StartQ <= GPIO_Start;
assign GPIO_LED_Ready = GPIO_StartQ;

  Hope this helps...

 

- Bob Elkind

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Summary:
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3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Participant
Participant
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Registered: ‎09-11-2010

> Can you verify that CLK is actually a working clock signal?

 

Based on the logic I posted which was converted to use edge of CLK, I don't think CLK is actually a working clock signal.

 

> is the CLK signal used anywhere else in the design?

 

Yes, CLK is used throughout about 30% of the design.

 

> Have you checked the source clock input signal to the FPGA?

 

No, I have not done that lately.  I did run the baseline design which does utilize the clock and at the time they worked fine.

 

>Did you copy the code for the PLL from the SP605 board baseline design, or is this a change from the baseline code?

 

I changed it from a PLL_ADV to a PLL_BASE to reduce the complexity and reduced the number of outputs from 5 to 3.  The design then uses these 3 clocks.

 

>I'm not a Verilog language authority, but I'm completely unfamiliar with the syntax 'TRUE

 I am using an include file which contains define statements to put text names to bit patterns.  Below is the definition of True.

    `define True 1'b1

 

The original intention of the code was to toggle the wire SearchNow to reset a FSM.  I added the LED to provide a visual cue that the code was actually running.

 

I am going to update the design to use the output from IBUFGDS as the clock for the LED to prove that the external clock is working.  If that is successful then the problem must be in the PLL_BASE.

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Instructor
Instructor
7,688 Views
Registered: ‎07-21-2009

>Did you copy the code for the PLL from the SP605 board baseline design, or is this a change from the baseline code?

 

I changed it from a PLL_ADV to a PLL_BASE to reduce the complexity and reduced the number of outputs from 5 to 3.  The design then uses these 3 clocks.

From my previous post:

You should post the clock signal path from input to PLL to distribution buffer.  The MAP warning message suggests a problem with the PLL instantiation.

- Bob Elkind

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Participant
Participant
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Registered: ‎09-11-2010

Maybe I am missunderstanding your request, but the clocking definitions were included in my original post. 

 

I did regenerate with the LED code being driven by the output from the IBUFGDS and the LED toggled as expected.  I think that shows that the 200Mhz clock signal is available on FPGA.  I will switch back to PLL_ADV and see if that resolves the issue.

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Instructor
Instructor
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Registered: ‎07-21-2009

Maybe I am missunderstanding your request, but the clocking definitions were included in my original post.

So right, I forgot to look there...  oops.

 

Hey, you didn't specify these PLL parameters in the code you posted (values consistent with the code you posted):

 

 (.BANDWIDTH         ("OPTIMIZED"),  // default is OPTIMIZED
.CLK_FEEDBACK ("CLKFBOUT"), // default is CLKFBOUT
.COMPENSATION ("INTERNAL") // default is SYSTEM_SYNCHRONOUS
.DIVCLK_DIVIDE (1), // default is 1

Also, I noticed you quoted a MAP warning message which referred to a PLL_ADV, but your posted code infers a PLL_BASE, not PLL_ADV.  I Don't know if that is "interesting" or not.

There are a number of info and warnings in the synth and Map reports.  The message below from the Map report is referencing the clock.  I looked up Compensation variable and did not find INTERNAL as an option for System_synchronous:

 

MapLib:841 - Changing COMPENSATION attribute from SYSTEM_SYNCHRONOUS to INTERNAL for PLL_ADV Project_CLKS/PLL_ADV.

 

 - Bob Elkind

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Summary:
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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Participant
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Registered: ‎09-11-2010

Thanks for your help.  I made sure that all of the parameters, inputs and outputs were defined for the PLL_BASE and I am now getting a clock signel.  I have a lot of debugging to do to ensure that the design is actually working but at least have something to work with.

 

Thanks again

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Instructor
Instructor
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Registered: ‎07-21-2009

For those who follow in your footsteps, would you please list the changes you made which got you up and running?

 

Thanks.

 

- Bob Elkind

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3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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Participant
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Registered: ‎09-11-2010

Here is the final code that seems to be working great.  For others that are new to FPGA's I would suggest utilizing the clocking wizard in Core generator.  Had I used it originally I would have saved a lot of time trying to determine the code and debugging it.

 

Thanks again for all the help.

 

 wire   osc_clk_ibufg;
 wire   CLKFBOUT;
 wire   CLKFBIN;
 wire        locked_unused;
 wire        clkout3_unused;
 wire        clkout4_unused;
 wire        clkout5_unused;
 wire   CLK_Bufg_in;
 wire   CLKM_Bufg_in;
 wire   ECLK_Bufg_in;
 (* clock_signal = "yes" *) wire CLK;
 (* clock_signal = "yes" *) wire CLKM;
 (* clock_signal = "yes" *) wire ECLK;
 
  
BUFG CLK_Buf (
 .O(CLK),
 .I(CLK_Bufg_in));
BUFG CLKM_Buf (
 .O(CLKM),
 .I(CLKM_Bufg_in));
BUFG ECLK_Buf (
 .O(ECLK),
 .I(ECLK_Bufg_in));
BUFG CLKFBOUT_Buf (
 .O(CLKFBIN),
 .I(CLKFBOUT));
 
 
 /* System Clock */
// IBUFG the raw clock input

IBUFGDS #(
  .DIFF_TERM("FALSE"),    // Differential Termination (Virtex-4/5, Spartan-3E/3A)
  .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
                          //   the buffer, "0"-"16" (Spartan-3E/3A only)
  .IOSTANDARD("LVDS_25")  // Specify the input I/O standard
) inibufg (
  .O(osc_clk_ibufg),  // Clock buffer output
  .I(SYSCLK_P),  // Diff_p clock buffer input (connect directly to top-level port)
  .IB(SYSCLK_N) // Diff_n clock buffer input (connect directly to top-level port)
);

 
PLL_BASE #(
 .BANDWIDTH("OPTIMIZED"),  // default is OPTIMIZED
   .CLK_FEEDBACK("CLKFBOUT"),   // default is CLKFBOUT  
 .COMPENSATION("SYSTEM_SYNCHRONOUS"),    // default is SYSTEM_SYNCHRONOUS  
 .DIVCLK_DIVIDE(1),            // default is 1
 .CLKFBOUT_MULT(2),
 .CLKFBOUT_PHASE(0.0),
 .CLKIN_PERIOD(5.0),
 .CLKOUT0_DIVIDE(16),
 .CLKOUT0_DUTY_CYCLE(0.5),
 .CLKOUT0_PHASE(0.0),
 .CLKOUT1_DIVIDE(8),
 .CLKOUT1_DUTY_CYCLE(0.5),
 .CLKOUT1_PHASE(0.0),
 .CLKOUT2_DIVIDE(16),
 .CLKOUT2_DUTY_CYCLE(0.5),
 .CLKOUT2_PHASE(180.0),
 .REF_JITTER(0.010000)

 ) Project_CLKS (
  .CLKFBOUT(CLKFBOUT),
    .CLKOUT0(CLK_Bufg_in),   // 25Mhz 0 Phase
    .CLKOUT1(CLKM_Bufg_in),  // 50Mhz 0 Phase
    .CLKOUT2(ECLK_Bufg_in),   // 25Mhz 180 Phase
  .CLKOUT3(clkout3_unused),
    .CLKOUT4(clkout4_unused),
    .CLKOUT5(clkout5_unused),
    .LOCKED(locked_unused),
    .RST(1'b0),
  .CLKFBIN(CLKFBIN),
    .CLKIN(osc_clk_ibufg)
    );

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Instructor
Instructor
4,998 Views
Registered: ‎07-21-2009

In a quick before/after comparison, the only difference I saw was inserting a BUFG in the CLKFBOUT => CLKFBIN connection.  The PLL attributes which were added were simply the default values, so they should not be the "fix".

 

Do I have this right?  If so, I point you UG382 (v1.4) top of page 34:

Designs with high-speed source synchronous outputs do not require exact timing delays
from the GCLK input to the I/O clock domain. When timing alignment is not required, the
PLL can use a dedicated feedback from
CLKFBOUT to CLKFBIN without the use of any
clock buffers
(Figure 1-17).

I'm glad you're up and running, but it isn't obvious to me what made the difference.

 

- Bob Elkind

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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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Participant
Participant
4,953 Views
Registered: ‎09-11-2010

I agree most of the changes were the defaults.  I added additional outputs but those were optimized away during XST.  The only thing that makes any sense as to why it is working now is definition of RST input.  I had left it off the original design and defined it as 0 in the latest.

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