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Observer asimons
Observer
7,669 Views
Registered: ‎11-19-2010

SP605 SDRAM Bandwidth

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I am trying to understand how much bandwidth there is between the FPGA and SDRAM on this board.  The SP605 hardware user guide states that there is 667 Mb/s bandwidth.  However, in the Spartan-6 Memory Controller Guide UG388, it says the Spartan 6 has 12.8 Gb/s bandwidth to DDR3 with a 16-bit bus, which I believe the SP605 uses.  Why is there this disconnect?  What am I missing?  Thanks!

 

Alan Simons

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Teacher eteam00
Teacher
9,919 Views
Registered: ‎07-21-2009

Re: SP605 SDRAM Bandwidth

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The documentation

 

The 'documentation' in this case is the SP605 Hardware User Guide UG526.  We (me, at least) are easily confused in this forum, so please don't spare essential details.

 

simply says 667 Mb/s memory bandwidth, which would be 83 MBytes / sec by some logic

 

A more correct specification is 667 MTransfers/sec.  Using a 16bit DRAM, this would translate to 1333 MBytes/sec.

 

I'm trying to specifically find what the maximum bandwidth this board can support is, but none of the docs just say it.

 

The answer, per UG526 version 1.6, is 1333 MBytes/sec.  This is based on the statement on page 13 of UG526:

"The SP605 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 667 Mb/s for DDR3 memory in a -3 speed grade device."

 

The User Guide leaves the x16 multiplication to the user.  Is this confusing?  Possibly, but most people using the SP605 board understand DRAM usage enough to figure it out.  For instance, 64-bit DIMM modules for PCs are specified and compared by both speed grade (e.g. DDR2-667, DDR3-1066) and transfer bandwidth (e.g. PC2-5300, PC3-8500).

 

Having said that, Xilinx updated the Spartan-6 datasheet (DS162) as of version 2.1 to increase the DDR3 'standard' guaranteed performance of -3 speed grade parts.  The current guaranteed spec is 800Mbits/sec (800MT/sec), per DS162 Table 25.

 

If you are starting a new design for the SP605 (which uses a -3 speed grade FPGA), using the current ISE (and MIG) software and speed files, the SP605 supports up to DDR3-800 operation (i.e. 1600 MBytes/sec).  The SP605 HW User Guide is out of date (incorrect) in this important and useful specification.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
13 Replies
Teacher eteam00
Teacher
7,666 Views
Registered: ‎07-21-2009

Re: SP605 SDRAM Bandwidth

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667 Mb/s bandwidth is the operating speed of the SP605 board design and SP605 board memory.

 

12.8 Gb/s bandwidth is the maximum memory clock speed (800 MHz) of the fastest speed grade Spartan-6 (-3) multiplied by 16 bits.  This is (more or less) a datasheet specification for the Spartan-6 family, not a specification for a specific circuit board implementation.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer asimons
Observer
7,662 Views
Registered: ‎11-19-2010

Re: SP605 SDRAM Bandwidth

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Now, the SP605 apparently has a 16-bit interface to SDRAM.  Does that mean I get 16 * 667 Mb/s?

 

Alan

 

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Teacher eteam00
Teacher
7,655 Views
Registered: ‎07-21-2009

Re: SP605 SDRAM Bandwidth

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Now, the SP605 apparently has a 16-bit interface to SDRAM.  Does that mean I get 16 * 667 Mb/s?

 

It means you can achieve *up to* 16 * 667Mb/sec transfer bandwidth between the FPGA and DRAM.

 

How often and how persistently you can realise this bandwidth is largely determined by the MCB, the DRAM, and your access pattern.  You should expect less than half that bandwidth for typical applications, and around 80% of that bandwidth for specialised applications (e.g. video) with highly structured addressing patterns.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer asimons
Observer
7,650 Views
Registered: ‎11-19-2010

Re: SP605 SDRAM Bandwidth

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My problem is reasoning with a coworker about memory bandwidth.  The documentation simply says 667 Mb/s memory bandwidth, which would be 83 MBytes / sec by some logic and this is what he is saying we can get.  I know from past experience that I got much more bandwidth than that on a Spartan-6 LT150X board.  I'm trying to specifically find what the maximum bandwidth this board can support is, but none of the docs just say it.  If there really is a "* 16" factor to the numbers, that's great.  I just want to see some doc that specifically says it.

 

Alan

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Xilinx Employee
Xilinx Employee
7,644 Views
Registered: ‎01-03-2008

Re: SP605 SDRAM Bandwidth

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Have your coworker look at Table 1-1 in the Spartan-6 MCB User Guide, UG388, that should clear up their misunderstanding.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Teacher eteam00
Teacher
9,920 Views
Registered: ‎07-21-2009

Re: SP605 SDRAM Bandwidth

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The documentation

 

The 'documentation' in this case is the SP605 Hardware User Guide UG526.  We (me, at least) are easily confused in this forum, so please don't spare essential details.

 

simply says 667 Mb/s memory bandwidth, which would be 83 MBytes / sec by some logic

 

A more correct specification is 667 MTransfers/sec.  Using a 16bit DRAM, this would translate to 1333 MBytes/sec.

 

I'm trying to specifically find what the maximum bandwidth this board can support is, but none of the docs just say it.

 

The answer, per UG526 version 1.6, is 1333 MBytes/sec.  This is based on the statement on page 13 of UG526:

"The SP605 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 667 Mb/s for DDR3 memory in a -3 speed grade device."

 

The User Guide leaves the x16 multiplication to the user.  Is this confusing?  Possibly, but most people using the SP605 board understand DRAM usage enough to figure it out.  For instance, 64-bit DIMM modules for PCs are specified and compared by both speed grade (e.g. DDR2-667, DDR3-1066) and transfer bandwidth (e.g. PC2-5300, PC3-8500).

 

Having said that, Xilinx updated the Spartan-6 datasheet (DS162) as of version 2.1 to increase the DDR3 'standard' guaranteed performance of -3 speed grade parts.  The current guaranteed spec is 800Mbits/sec (800MT/sec), per DS162 Table 25.

 

If you are starting a new design for the SP605 (which uses a -3 speed grade FPGA), using the current ISE (and MIG) software and speed files, the SP605 supports up to DDR3-800 operation (i.e. 1600 MBytes/sec).  The SP605 HW User Guide is out of date (incorrect) in this important and useful specification.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Teacher eteam00
Teacher
7,616 Views
Registered: ‎07-21-2009

Re: SP605 SDRAM Bandwidth

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I've opened webcase #888616 to update UG526, page 13, as follows:

 

UG526 v1.6, page 13 includes the following statement:


"The SP605 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 667 Mb/s for DDR3 memory in a -3 speed grade device."

As of DS162 v2.1, DDR3 memory (MCB) performance in -3 speed grade parts is 800Mb/s, not 667Mb/sec -- and there is no distinct performance range or setting for DDR3 memory (only for DDR2 memory).

Also, because the SP605 DRAM is 16 bits wide, the 800 (or 667) Mb/sec figure is misleading. SP605 DRAM bandwidth should be re-stated as either 800 MT/sec (transfers/sec) or 1600 MB/sec (bytes/sec).

Change UG526 page 13 text to read:
"The SP605 board supports memory controller block (MCB) performance of 800 MT/s (or 1600 MBytes/sec with 16-bit memory) for DDR3 memory in a -3 speed grade device."

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher eteam00
Teacher
7,589 Views
Registered: ‎07-21-2009

Re: SP605 SDRAM Bandwidth

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Pursuant to webcase #888616,

 

CR 622620 is filed against UG526

 

This should update UG526 to reflect that SP605 board supports up to DDR3-800 operation.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Xilinx Employee
Xilinx Employee
7,580 Views
Registered: ‎02-02-2010

Re: SP605 SDRAM Bandwidth

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The wording of UG526 bears revision but it's incorrect to state that an SP605 can be guaranteed at 800MT/s. 

 

The SP605 is tested at 667MT/s.  At the time the doc was written, it spoke for the MCB accurately but now it simply speaks for the board itself.

 

ETA: http://www.xilinx.com/support/answers/35818.htm

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Teacher eteam00
Teacher
3,822 Views
Registered: ‎07-21-2009

Re: SP605 SDRAM Bandwidth

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The wording of UG526 bears revision but it's incorrect to state that an SP605 can be guaranteed at 800MT/s.

 

I believe that might change, soon.  This is the point of the webcase and CR.

 

The SP605 is tested at 667MT/s.  At the time the doc was written, it spoke for the MCB accurately but now it simply speaks for the board itself.

 

It should still speak for the MCB.  MCB performance has been updated, and a board which

 

  • uses the -3 speed grade Spartan-6 device
  • uses DDR3 device which supports DDR3-800 operation
  • is designed to the guidelines of UG388
  • uses a MIG-generated MCB-based controller
  • otherwise complies with all other DS621 requirements (power supply, etc.)

should be guaranteed by Xilinx to support DDR3-800.

 

Xilinx' performance guarantee is not based on characterisation of each custom board design, it is based on characterisation of the components (see list above) and design requirements which are used to build the custom board design.  Xilinx customers rely on this guarantee.  Why is the SP605 board any different?

To not extend the SP605 spec represents a disbelief in Xilinx' own datasheet guarantees.  This would -- and should -- raise strong concerns in designers (i.e. customers).

 

Should the SP605 be tested at DDR3-800?  Absolutely.

 

Do you think re-rating the SP605 board without testing is a leap of faith?  If so, it is the same leap of faith Xilinx is asking its customers to take when basing their designs on Spartan-6 devices, Xilinx specs, and Xilinx guidelines.

 

The AR to which Amandaw linked refers to standard vs. enhanced performance distinction for DDR2 (and only DDR2) MCB controllers (see DS162, Table 25). SP605 uses DDR3, not DDR2.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Xilinx Employee
Xilinx Employee
3,809 Views
Registered: ‎01-03-2008

Re: SP605 SDRAM Bandwidth

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> Why is the SP605 board any different?

 

The SP605 board is a system and not just the silicon and the DDR3 performance is for the entire system.  When we completed all of the testing on the board is was done with the 667 Mbps data rate and all of the reference designs and documentation are geared to this data rate. 

 

Much later after additional characterization and testing of the Spartan-6 MCB the performance levels were raised to 800 Mbps.   We considered the work involved to accomplish the design updates, re-testing, test program updates, documentation rewrites and reference design releases and made the decision to leave the SP605 at the 667 Mbps level. 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Teacher eteam00
Teacher
3,806 Views
Registered: ‎07-21-2009

Re: SP605 SDRAM Bandwidth

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Ed,

 

Agreed that the reference (firmware) design, and docs for the reference (firmware) designs, are DDR3-667.

 

The SP605 board should support new (customer-supplied) FPGA designs -- based on MIG/MCB -- which run at DDR-800 speed.  In other words, SP605 circuit board should be suitable as a hardware platform for developing and proving DDR3-800 designs.

 

I suspect (just guessing) that a re-MIG-gen of the reference SP605 design should also run DDR3-800 with little or no problems.  Unlike the MIG-generated DRAM controllers targeted for Virtex devices, there is no fixed clock frequency relationship between the controller's UI port(s) and the DRAM.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher eteam00
Teacher
3,800 Views
Registered: ‎07-21-2009

Re: SP605 SDRAM Bandwidth

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Ed,

 

The last thing I want to do in life is to annoy you, and I suspect that I'm on the verge of doing just that.  It's not my intent, for what it's worth.

 

Proposition:

 

If the SP605 team had determined from the outset to design a DDR3-800 capable board, with the current DS621 specifications in hand, not a single trace of the SP605 circuit board would have turned out differently from the SP605 which is currently documented as a DDR3-667 capable board.

 

The same design rules, layout rules, and components would have been used.

 

I concede the point that it is foolhardy to specify a product capability which has not been tested to the standards of the firm.  I wouldn't do it, and no-one should expect Xilinx to do it (my previous posts in this thread notwithstanding).

 

This raises an interesting question, one which likely extends beyond the original intent and purpose of this thread.  I'll try to articulate this question clearly, but I may not be fully up to the task, so I beg your indulgence.

 

A hypothetical designer is developing a product which depends upon DDR3-800 capability, and incorporates the same pieces and bits specified and described by Xilinx docs as the SP605.  The company developing this product does not have the capabilities or resources to test worst-case Spartan-6 silicon and worst-case DRAM silicon for DDR3-800 competency.  Any test regime short of full characterisation suites is arguably incomplete.

 

Can this company honestly warrant its product to DDR3-800 performance, based firmly on the assurance: that Xilinx performed the rigorous characterisation testing of the design components used to construct the final product?  Can the company claim with confidence that its product meets performance specs, on the basis of 'correct-by-construction' ?  If not, then what testing is this company obligated to perform before committing its treasure and reputation to production?

 

In short, what are designers to make of the DS621 specifications and UG388 guidelines, as they apply to their own Spartan-6 based board designs?

 

Thank you for your patience.  I understand your viewpoint, and I hope I've expressed mine clearly enough that you understand my viewpoint as a designer.  In large part, I suspect, our interests are much the same.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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