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Participant manish.ranade
Participant
8,979 Views
Registered: ‎05-12-2009

SP605 and FMC XMC105 interface

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Hello,

I have SP605 and FMC XMC105 debug card. 

Planning to use programmable frequency generator on FMC -  Si570, which can be programmed over I2C initiated through SP6 on SP605.

I am not clear on voltage levels of this interface.

SP6 on SP605:

VCCO for banks 0, 1, 2 is 2.5V   -- Most I/Os on FMC covered in this. Hence should follow 2.5V signaling - LVCOS25 and LVDS25

VCC of Si570 on FMC is 3.3V 

This make 3.3V I2C bus interfaced with 2.5V I/Os on SP6 and 

Generated LVDS33 clock from Si570 interfaced to 2.5V (LVDS25) I/O on SP6   

 Are these connections electrically safe to use?

 

Extension to same doubt,

Can TMDS33 signal be safely connected to SP6 LVDS25  I/O pair as input (with VCCO = 2.5V in subsequent bank)

 

Thanks,

Manish

 

 

 

 

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Participant manish.ranade
Participant
11,266 Views
Registered: ‎05-12-2009

Re: SP605 and FMC XMC105 interface

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Hi mcgett,

 

Thanks for answering LVDS and TMDS related issues,

 

but for IIC,

I traced I2C lines in FMC and SP605 schematics. Didn't find voltage translator

The path for one :

FMC_[U2 pin8]@IIC_SCL--->FMC_[J17 pinC30]--------SP605_[J2 pinC30]@IIC_SCL_MAIN--->SP605_J45-->SP605_[DUT pinT21]

Probably you are referring to other set of IIC lines related to DVI connector which has translators.

 

Actually, looking at DS162 table 9, its clear no translation is needed.  Especially VIH_max for LVCOMS25 and LVCMOS33 is 4.1V, hence I believe compatibility and safety is both assured, which answers my original question

 

Bob, thanks for DS162 reference!

 

Manish

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Xilinx Employee
Xilinx Employee
8,965 Views
Registered: ‎01-03-2008

Re: SP605 and FMC XMC105 interface

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This make 3.3V I2C bus interfaced with 2.5V I/Os on SP6 and

 

There is a level translator on the SP605 I2C lines to handle this conversion.

 

Generated LVDS33 clock from Si570 interfaced to 2.5V (LVDS25) I/O on SP6   

 Are these connections electrically safe to use?

 

LVDS is LVDS it doesn't matter what the VCCO level is that drives it.  In all cases the common mode will be 1.25V.

 

Can TMDS33 signal be safely connected to SP6 LVDS25  I/O pair as input (with VCCO = 2.5V in subsequent bank)


The Spartan-6 SelectIO User Guide UG381 documents the VCCAUX and VCCO compatability between different standards.  Looking at Table 1-5 shows that TMDS_33 inputs have a requirement for VCCAUX=3.3 and VCCO=Any.  The SP605 has a VCCAUX of 2.5V so it is not compatible with TMDS_33 inputs.

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Teacher eteam00
Teacher
8,958 Views
Registered: ‎07-21-2009

Re: SP605 and FMC XMC105 interface

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Ed,

 

My post was full of incorrect and incomplete answers, so I just deleted it.  Thanks for the corrections.

 

- Bob

SIGNATURE:
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Participant manish.ranade
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11,267 Views
Registered: ‎05-12-2009

Re: SP605 and FMC XMC105 interface

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Hi mcgett,

 

Thanks for answering LVDS and TMDS related issues,

 

but for IIC,

I traced I2C lines in FMC and SP605 schematics. Didn't find voltage translator

The path for one :

FMC_[U2 pin8]@IIC_SCL--->FMC_[J17 pinC30]--------SP605_[J2 pinC30]@IIC_SCL_MAIN--->SP605_J45-->SP605_[DUT pinT21]

Probably you are referring to other set of IIC lines related to DVI connector which has translators.

 

Actually, looking at DS162 table 9, its clear no translation is needed.  Especially VIH_max for LVCOMS25 and LVCMOS33 is 4.1V, hence I believe compatibility and safety is both assured, which answers my original question

 

Bob, thanks for DS162 reference!

 

Manish

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Teacher eteam00
Teacher
8,935 Views
Registered: ‎07-21-2009

Re: SP605 and FMC XMC105 interface

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Probably you are referring to other set of IIC lines related to DVI connector which has translators.

The FETs on page 16 of the schematic are not voltage translators.  They are there to isolate the FPGA I2C pins from the DVI connector when the FPGA is not powered.

 

I agree with your no-harm assessment of 3.3V on Spartan 6 IO pins.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Participant manish.ranade
Participant
8,930 Views
Registered: ‎05-12-2009

Re: SP605 and FMC XMC105 interface

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Hi Bob,

about

"The FETs on page 16 of the schematic are not voltage translators.  They are there to isolate the FPGA I2C pins from the DVI connector when the FPGA is not powered."

 

When Sp605 connected to DVI monitor and:

 FPGA is powered ON and  DVI monitor is ON, these lines to should be +5V tolerant.

This makes +5V (monitor side) and LVCOMS25 @FPGA  side.

 

 

Does this FET act as translator too or always isolates these I/Os from DVI world of +5V?

 

Manish

 

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Xilinx Employee
Xilinx Employee
8,915 Views
Registered: ‎01-03-2008

Re: SP605 and FMC XMC105 interface

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I traced I2C lines in FMC and SP605 schematics. Didn't find voltage translator

 

Sorry, I was writing from memory and confused different boards.  As already noted in the thread the S-6 IOs are 3.3V tolerant so this won't be an issue.

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Teacher eteam00
Teacher
8,900 Views
Registered: ‎07-21-2009

Re: SP605 and FMC XMC105 interface

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Bob:

"The FETs on page 16 of the schematic are not voltage translators.  They are there to isolate the FPGA I2C pins from the DVI connector when the FPGA is not powered."

Manish:

Does this FET act as translator too or always isolates these I/Os from DVI world of +5V?

Manish, you are correct.  The FETs would shut off as the signal level on the FPGA pin side approached the gate voltage (2.5V).  So yeah, the FET serves as a voltage translator.

 

As an interesting (in a geeky sort of way) side note, if you google FDS331N (the Fairchild Nch FET we are discussing), it's interesting that one of the provided links is this one: http://www.xilinx.com/products/boards/ml505/datasheets/NDS331N.pdf

 

I guess Xilinx (and its customers) must have a longterm relationship with this particular FET.  :)

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant manish.ranade
Participant
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Registered: ‎05-12-2009

Re: SP605 and FMC XMC105 interface

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Bob:

"Manish, you are correct.  The FETs would shut off as the signal level on the FPGA pin side approached the gate voltage (2.5V).  So yeah, the FET serves as a voltage translator."


The signals here (SCL, SDA)  are bidirectional in theory. Those are from DDC channel lines of DVI connector.


This translation scheme works well for bi-directional line?


Am I missing something...  

 

Manish

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Teacher eteam00
Teacher
8,805 Views
Registered: ‎07-21-2009

Re: SP605 and FMC XMC105 interface

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The DDC SCL and SDA lines can be pulled up to any conceivable voltage.  Amazingly enough, the pullup voltage is not defined in the HDMI spec or the DVI spec, nor is a pullup voltage proscribed in the Philips I2C specification.  In common practice (the resort of choice when specifications are lacking - see ISA bus), the pullup voltage is likely to be (nominally) either 5V or 3.3V.

 

When SDA or SCL is LOW, the protective nFETs in the SP605 (and similar) schematics are transmissive.  Gate-source voltage is positive (roughly 2V), which makes all the difference in the world.  Life is good.

 

When SDA or SCL is high, the nFET gate-source voltage will be 0 or negative, and the nFET will be non-transmissive.  The two "ends" of the nFET (source and drain) will be isolated from one another.  A pullup to VCCO on the FPGA side (R61 and R63 on page 17 of the SP605 schematics) will determine the HIGH voltage level seen by the FPGA (and other on-board conections).  A pullup to 3.3V or 5V at the HDMI or DVI "sink" (or display) (or R59 and R60 on page 16 of the SP605 schematics) will determine the HIGH voltage level at the SP605 DVI connector.

 

So...  the NDS331N nFETS are primarily protective devices which also, by way of pullups on either side of the FETs, facilitate "voltage translation" (in a somewhat loose application of the term).

 

There....  I've told you everything I know... and more!

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Participant manish.ranade
Participant
2,399 Views
Registered: ‎05-12-2009

Re: SP605 and FMC XMC105 interface

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Thanks Bob,

Yes in-deed, you have explained it all..  

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