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Participant liangr
Participant
7,214 Views
Registered: ‎12-22-2009

[SPARTAN6]-[SP605 Evaluation Kit ] GPIO User SMA

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Dear all,

 

I am a beginner of uing Xilinx board and I am looking for a platform to verify transceiver design.

 

I found SP605 may satisfy my request but I have some question concerning this evaluation board SP605.

 

There are 10 SMA connectors on board and according to user guide ug526.pdf figure1-2 , the USER_SMA_CLOCK_N/P (7C) and USER_SMA_GPIO_N/P (16D) are used as well. Are they bi-directional or output only?

 

Since the schematic has no input DC block cap, I am not sure about their direction.

 

And are the ports 8 (except for the reference clock), 7C and 16D support up to 3.125GHz signal?

 

Thank you in advance for the support!

 

 

/BR

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Xilinx Employee
Xilinx Employee
8,906 Views
Registered: ‎01-03-2008

Re: [SPARTAN6]-[SP605 Evaluation Kit ] GPIO User SMA

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The 10 SMAs are connected to the FPGA pins, but not all FPGA pins are bi-directional.  The 4 SMAs that you referenced are connection to normal IO and can be used as either inputs or outputs.

 

DC block/AC coupling capacitors are not just for inputs.  PCIexpress for inputs defined their use on the transmitters.

 

The performance of any board is predominately determined by the silicon that is used.  In the case of SP605 the device is a XC6SLX45TFG484-3 the MGTs in this device/speed grade are capable of 3.125 Gbps operation.

 

 

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Xilinx Employee
Xilinx Employee
8,907 Views
Registered: ‎01-03-2008

Re: [SPARTAN6]-[SP605 Evaluation Kit ] GPIO User SMA

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The 10 SMAs are connected to the FPGA pins, but not all FPGA pins are bi-directional.  The 4 SMAs that you referenced are connection to normal IO and can be used as either inputs or outputs.

 

DC block/AC coupling capacitors are not just for inputs.  PCIexpress for inputs defined their use on the transmitters.

 

The performance of any board is predominately determined by the silicon that is used.  In the case of SP605 the device is a XC6SLX45TFG484-3 the MGTs in this device/speed grade are capable of 3.125 Gbps operation.

 

 

------Have you tried typing your question into Google? If not you should before posting.
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Participant liangr
Participant
7,050 Views
Registered: ‎12-22-2009

Re: [SPARTAN6]-[SP605 Evaluation Kit ] GPIO User SMA

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Thanks a lot McGett.

 

I once remember that the GPIO output is connected to a parallel-to-serial register and the bit width of the register is 8bit, however, when output the bits in serial to GPIO, 1 of the 8 bits is used as redundancy check bit so only 7/8 speed of 3.125G can be reached. Is that true?

 

The place I found the speed is from xtp066.pdf (page 20 and 22) and the speed of the IO is 2.5Gbps with PRBS of 7 bits.

 

I could not find any detailed information from the user guide so I hope it is possible to serial output serial bit signal from the GPIO SMA port at true 3.125GHz.

 

Thank you.

 

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Xilinx Employee
Xilinx Employee
7,040 Views
Registered: ‎01-03-2008

Re: [SPARTAN6]-[SP605 Evaluation Kit ] GPIO User SMA

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I don't quite understand why you are using the term "GPIO".  GPIO is a term that is used with microprocessor and refers to pins that can be individual read or written by software for bit-banging applications.

 

FPGAs have one of three types of IO

  - Dedicated IO - These are fixed function pins such as JTAG, configuration, DXP/DXN etc

  - Select IO - These can be used as inputs, outputs or bi-directional and support a wide range of IO standards

  - MGT IO - These are connected to Multi-Gigabit Transceivers and are either TX, RX or reference clock inputs

 

Select IO can not operate at 3.125 Gbps

MGT IO can operate at 3.125 Gbps in Spartan-6

 

Gbps is not the same as GHz

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Participant liangr
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Registered: ‎12-22-2009

Re: [SPARTAN6]-[SP605 Evaluation Kit ] GPIO User SMA

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Hi McGett,

 

Thank you for the answering, since there are 10 SMAs available on the board, I hope I can know more about the use of these ports.

 

From the user guide, (ug526.pdf, page 10),  SMAs are grouped into 8, 7c and 16d 3 groups,

 

1. For group 8, they are MGT IOs and we have differential RX TX pair and REFCLK, is REFCLK bidirectional or only input reference?

 

2. And for group 7c, they are user SMA clock p/n according to the schematics and are they capable of 3.125Gbps operation? And what is the direction of group 7c?

 

3. For group 16d, they are USER GPIO and according to your reply, they are select IO and can not work at 3.125Gbps, am I right?

 

Thank you again for the answerings.

 

 

 

 

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Xilinx Employee
Xilinx Employee
7,009 Views
Registered: ‎01-03-2008

Re: [SPARTAN6]-[SP605 Evaluation Kit ] GPIO User SMA

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> 1. For group 8, they are MGT IOs and we have differential RX TX pair and REFCLK, is REFCLK bidirectional or only input reference?

 

The Spartan-6 GTP User Guide, UG386, will answer this question.

 

> 2. And for group 7c, they are user SMA clock p/n according to the schematics and are they capable of 3.125Gbps operation? And what is the direction of group 7c?

 

My first reply in this thread and my reply before this one will answer this question.

 

> 3. For group 16d, they are USER GPIO and according to your reply, they are select IO and can not work at 3.125Gbps, am I right?

 

Yes

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