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Explorer
Explorer
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Registered: ‎03-16-2013

Silicon Labs Si5324 jitter attenuator output is always high when i download my code

with demo kc705-si5324-rdf0192-2013.2-c, i configur the si5324that it  can output a 245.76MHz CLK,but ,when i download my code ,it output high,so i want to know whether the fpga do not write the register map into eeprom when i use demo code

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Moderator
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Registered: ‎01-15-2008