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Registered: ‎06-02-2014

Simulate DDR3 signals with ZYNQ and MT41J128M16JT

Hi. I'm starting with DDR3 designs and I decided to make some simulation first. I have the IBIS models of ZYNQ and MT41J128M16JT and I'm using Hyperlynx to simulate. I was looking a ZYNQ design from Digilent called ZyBo. I get the schematic and try to reproduce the DDR3 part to simulate signal integrity with Hyperlynx Line sim 8.0. For example, I started with Adress signals. In the schematic, the connection is like the one in the first picture.

adrres ddr3.png

I made my model in Hyperlynx linesim:

linesim ddr3.png

I set the TL to 40 Ohms because the ZyBo manual says. The model I'm using to ZYNQ is SSTL15_S_PSDDR, according to Xilinx specifications in this AR http://www.xilinx.com/support/answers/46871.html. I simulate for a frequency of 525MHz (Maximum frequency supported by ZyBo) and I get this eye pattern:

ddr simulation.png


I'm writing this post because I think that I'm doing something wrong. The waveform is very distorted in my opinion. I can't believe that the ZyBo DDR3 has this poor signal integrity. Or this is a possible waveform? Can someone help me with this? Thanks



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