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Visitor
Visitor
7,536 Views
Registered: ‎04-17-2014

Spartan 3AN fractal demo project UCF file

Hi all, 

 

on my Spartan 3AN started board I wanted to run fractals demo program, so I downloaded the source code from  

http://www-user.rhrk.uni-kl.de/~alles/fpga/  as reported in doc. "s3ask_demo.pdf".

 

However, reading the UCF of the project, it looks like the FPGA package is a TQFP or PQFP

rather than a BGA, in facts pins are all in Pxxx format (as below reported). 

This unless each pin in a BGA has a conventional number besides the usual label: <letter><number>.

 

Does anyone have a UCF for this project in the BGA form?

 

Thanks

Alberto

 

NET "ms_clk" LOC ="P133";
NET "ms_data" LOC = "P132";
NET "clk_pad" LOC = "P79";
#NET "led" LOC = "P128";
NET "rst" LOC = "P130";
#NET "button1" LOC = "P130";
#NET "button2" LOC = "P131";
NET "rgb<10>" LOC = "P182";
NET "rgb<11>" LOC = "P181";
NET "rgb<12>" LOC = "P180";
NET "rgb<13>" LOC = "P178";
NET "rgb<14>" LOC = "P176";
NET "rgb<5>" LOC = "P175";
NET "rgb<6>" LOC = "P172";
NET "rgb<7>" LOC = "P171";
NET "rgb<8>" LOC = "P169";
NET "rgb<9>" LOC = "P168";
NET "rgb<0>" LOC = "P167";
NET "rgb<1>" LOC = "P166";
NET "rgb<2>" LOC = "P165";
NET "rgb<3>" LOC = "P162";
NET "rgb<4>" LOC = "P161";
NET "hsync" LOC = "P156";
NET "vsync" LOC = "P155";

 

 

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Xilinx Employee
Xilinx Employee
7,533 Views
Registered: ‎07-11-2011

Hi,

 

Please check Page -63 of below UG, I think it lists pin locations for each section

http://www.xilinx.com/support/documentation/boards_and_kits/ug330.pdf

 

 

Hope this helps

 

 

Regards,

Vanitha

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Visitor
Visitor
7,486 Views
Registered: ‎04-17-2014

Thanks Vanitha for your suggestion, 

 

however what is strange in the UCF I posted is that

there are 15 channels assigned to the RGB control,

while there are only 12 channels reported in the UG.

 

Regards,

Alberto

 

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