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Registered: ‎03-29-2011

Spartan-3E FPGA Master serial Mode

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Hi I am using SPARTAN-3E and XCF04S  in my design to generate triangle waveforms using DAC. I want to use FPGA in master serial mode. 

 

In user guide, it is mentioned that in FPGA Master serial mode, FPGA will generate cclk using internal oscillator. It means FPGA has an internal oscillator ? , I mean no need to connect any crystal oscillator external to the FPGA ( No need to connect  a 50 MHz clock  to GCLK10 like in starter kit ?)

 

I am beginner in using FPGAs. Please advice me.

 

 

Thanks,

Siva

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Instructor
Instructor
4,488 Views
Registered: ‎07-21-2009

Re: Spartan-3E FPGA Master serial Mode

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Every Xilinx FPGA has an oscillator which can generate a clock for "master" configuration modes, used for the CCLK output clock.  For some (not all) FPGA families, this oscillator can be available for use after configuration has completed, when your design is operating in the FPGA.  For example, in the case of Spartan-3e, see DS312 (v3.8) page 112:

The CCLK configuration clock is active during the FPGA configuration process. After configuration completes, the CCLK oscillator is automatically disabled unless the Bitstream Generator (BitGen) option Persist=Yes. 

Note that the CCLK oscillator is spec'd to have a tolerance (variability) of up to +/- 50% !!

 

Note that the connections of CCLK for configuration may make this "free" oscillator unusable after configuration has completed.  You may not want the SPI clock to your flash memory running freely, for example.

 

Check the FPGA docs for the FPGA you plan to use.  The DCM (or MCM or MMCM) may have a frequency synthesizer capability.  Looking at the Spartan-3e datasheet, I believe a clock input is required for frequency synthesis.  The Spartan-6 family DCM has a free-running oscillator mode which does not require an external clock source.  Depending on which FPGA family you are using, you may not need an external clock source... but you may want one.  An external clock source is likely to be much more accurate and more stable than an on-chip free-running frequency synthesizer.  Check the FPGA family datasheet for synthesizer accuracy/stability specs.

 

Recommendation:  If you are designing a custom FPGA board, include in your design a provision for an external clock source connected to a GCLK FPGA pin.  You don't have to use it (or populate it on the board), but it will come in handy if you realise that it is indeed needed.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

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Instructor
Instructor
4,489 Views
Registered: ‎07-21-2009

Re: Spartan-3E FPGA Master serial Mode

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Every Xilinx FPGA has an oscillator which can generate a clock for "master" configuration modes, used for the CCLK output clock.  For some (not all) FPGA families, this oscillator can be available for use after configuration has completed, when your design is operating in the FPGA.  For example, in the case of Spartan-3e, see DS312 (v3.8) page 112:

The CCLK configuration clock is active during the FPGA configuration process. After configuration completes, the CCLK oscillator is automatically disabled unless the Bitstream Generator (BitGen) option Persist=Yes. 

Note that the CCLK oscillator is spec'd to have a tolerance (variability) of up to +/- 50% !!

 

Note that the connections of CCLK for configuration may make this "free" oscillator unusable after configuration has completed.  You may not want the SPI clock to your flash memory running freely, for example.

 

Check the FPGA docs for the FPGA you plan to use.  The DCM (or MCM or MMCM) may have a frequency synthesizer capability.  Looking at the Spartan-3e datasheet, I believe a clock input is required for frequency synthesis.  The Spartan-6 family DCM has a free-running oscillator mode which does not require an external clock source.  Depending on which FPGA family you are using, you may not need an external clock source... but you may want one.  An external clock source is likely to be much more accurate and more stable than an on-chip free-running frequency synthesizer.  Check the FPGA family datasheet for synthesizer accuracy/stability specs.

 

Recommendation:  If you are designing a custom FPGA board, include in your design a provision for an external clock source connected to a GCLK FPGA pin.  You don't have to use it (or populate it on the board), but it will come in handy if you realise that it is indeed needed.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

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3,583 Views
Registered: ‎03-29-2011

Re: Spartan-3E FPGA Master serial Mode

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Thank you for the details.:smileyhappy:

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