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Newbie
Newbie
32,000 Views
Registered: ‎04-03-2008

Spartan-3E Starter Kit Board ADC

 Anybody worked with ADC. Has  anybody a program on VHDL for ADC. Help me to find a code on VHDL for ADC. Please. Help me! Thank you.
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22 Replies
dclemmensen
Adventurer
Adventurer
31,979 Views
Registered: ‎12-29-2007

One If the starter kit reference designs uses the ADC. see:
   http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
This is a PicoBlaze-based design.

Even if you decide to create a design of your own (say, based on a state machine) you should look at the Picoblaze design anyway, and you should also go ahead and implement it as an excersize (it takes about ten minutes.) The ADC shares the SPI bus with several other devices, and the other devices must all be explicitly de-selected to prevent them from interfereing with the ADC. The Spartan 3E Starter Kit user guide gives the wrong sense for the de-select of the platform flash. The reference design uses the correct sense for this de-select.
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alexgiul
Explorer
Explorer
31,929 Views
Registered: ‎02-18-2008

Hi,
I've developed this wrapper in VHDL...I don't if it's the last version but there are all of thing to connect the spartan3e adc/amp to fpga
 
I hope it's usefull for you...
jseith
Visitor
Visitor
31,880 Views
Registered: ‎11-15-2007

Thanks I've been looking for help on this for a long time. Do you have any documentation for it?
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krunal_h_bhavsar
Participant
Participant
31,806 Views
Registered: ‎09-21-2007

hi.......I tried to implement your ADC code........but while defining ucd it shows error of could not parse........can u give me details......because I works on Verilog and not that much familier with VHDL. So please help me........
 
Regards,
krunal
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jermore
Visitor
Visitor
31,777 Views
Registered: ‎04-16-2008

if you could please give some notes on what each input/output is meant to represent it would be really helpful in trying to develop the pinout needed. Thank you so much!
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alexgiul
Explorer
Explorer
31,580 Views
Registered: ‎02-18-2008

Hi,

 

Port (

clk50 : in STD_LOGIC;

ce_amp : in STD_LOGIC;

start_conv : in STD_LOGIC;

SPI_MISO : in std_logic; --adc

CONV : out STD_LOGIC; --adc

ADC1 : out std_logic_vector(13 downto 0) := (others => '0');

ADC2 : out std_logic_vector(13 downto 0) := (others => '0');

gain : in std_logic_vector(7 downto 0);

AMP_CS : out STD_LOGIC;

MOSI : out STD_LOGIC; -- amp

SCK : out STD_LOGIC

);

according to the spartan3e guide, I've defined the in/out port :

clk50 is the system clock;

start_conv : is the signal to start the conversion

SPI_MISO is the feedback ( if I rember well)

CONV : this signal assert the end of conversion

ADCx is the value converted

gain is the gain to be setted on the amp.

The last 3 lines are the "real" signals connected to amp + adc.

 

The rest of code is a finite state machine with 3 process:

 

the first is where I check the various condition to perform the right timing and controll to the amp and adc

 

the second and third is the "assignation" process where I write/read the value on the to/from the adc.

 

If you have other question,

my mail is alexgiul@hotmail.com

 

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fsalomon
Visitor
Visitor
23,470 Views
Registered: ‎06-22-2009

Hi. I'm begginer in the fpga world, and I have a doubt. Sorry if I'm wrong, please let me know.
In the code ADC_AMP.vhd, I think the following code is not right:

   
    when START =>
        AMP_CS <= '0';
        index1 := 7; -- 8 bit value
   

    when START2 =>
        MOSI <= gain(index1);
    ...
    when LO_DUMMY =>   
        MOSI <= gain(index1);
        index1 := index1-1;
       
In this case, the slave (the programmable amplifier) takes the bit gain(7) in two occasions (in the first HI state -after START2 state- and in the second HI state -after the first LO_DUMMY state-), and it never takes the bit gain(0), so there is an error. Is it true what I say?
I'm working with the Spartan 3AN Starter Kit.
Thanks a lot!

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alexgiul
Explorer
Explorer
23,452 Views
Registered: ‎02-18-2008

Hi,

 

this is the latest version of my core.

 

Inside the package I have put:

    1) a model for programmable amplifier

    2) a model for ADC

 

The core for sending data througth RS232

A simple testbench.

 

I design it on Spartan3E Starter KIT: some people have used it succefully, but I think there are some changes to do when working with Starter Kit 3AN,

 

for example it's possible that there are some differences between how I  disable the strataflash...

 

I'm glad if you return some feedback and correction to the code.

 

 

 

 

 

bloodninja
Visitor
Visitor
23,123 Views
Registered: ‎07-09-2009

Hi,

 

Thanks for your code, but I can't get it to work no matter what I've tried. I've been using the adc2.vhd on the latter rar-package. I modified it a little, I changed the following two rows in the entity declarement

  ADC0 : out std_logic_vector(13 downto 0) := (others => '0');  
  ADC1 : out std_logic_vector(13 downto 0) := (others => '0');   

 

to (in architecture declarement, before the "begin")

    signal ADC0 : std_logic_vector(13 downto 0) := (others => '0'); 
    signal ADC1 : std_logic_vector(13 downto 0) := (others => '0');

 

since I want to use at least ADC0 straight in the vhdl-file as an input too.

 

My goal is to control an another device with J4 outputs, which are working fine when using buttons or so, but I'd like to automatize controlling depending on the analog input. Signal ADC0 seems to be just zeros now. My setup works correctly with the Picoblaze Amp ADC Control -example, but I'd like to complete the project without using Picoblaze. I'm new to FPGA-designs and VHDL. Can you help me?

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alexgiul
Explorer
Explorer
13,489 Views
Registered: ‎02-18-2008

Hi,

 

you can send me your project and I take a look on your code...

 

What king of problem you find in compiling my sources? 

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rupenman436
Observer
Observer
12,800 Views
Registered: ‎12-24-2009

I run the code adc2.vhd on Spartan 3E board but I couldn't get the correct output. I place 14 output to the LEDs using expansion connector and almost all the LED turned ON and the output don't respond to the change in input voltage.

 

So, I slightly modified ur code.But what I got the problem is there were numbers of warnings like

"D:/Sugan/ise/adc_teest/adc.vhd" line 49: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:

   <SPI_MISO>" 

 

and

"Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved."

 

Input <rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <chip_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 

even though  I place those parameters in sensitivity list and used them in the code for finite state machine.

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bassman59
Historian
Historian
12,790 Views
Registered: ‎02-25-2008


rupenman436 wrote:

I run the code adc2.vhd on Spartan 3E board but I couldn't get the correct output. I place 14 output to the LEDs using expansion connector and almost all the LED turned ON and the output don't respond to the change in input voltage.

 

So, I slightly modified ur code.But what I got the problem is there were numbers of warnings like

"D:/Sugan/ise/adc_teest/adc.vhd" line 49: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:

   <SPI_MISO>" 

 

and

"Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved."

 

Input <rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <chip_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 

even though  I place those parameters in sensitivity list and used them in the code for finite state machine.


So you placed the two ports on the sensitivity list of some process somewhere -- but are they actually USED in the process?

----------------------------Yes, I do this for a living.
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Anonymous
Not applicable
12,182 Views

Hello;

 

This is an old subject; but maybe someone can help me... I need to use ADC on spartan3E. I have used the adc2.rar source but I couldn't be successful to implement it. Is there anyone who use this code successfully and could you explain how it works?

 

Thank you:)

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aferreira
Newbie
Newbie
11,267 Views
Registered: ‎09-30-2010

Hi,

 

 

I have the same problem. What is the problem?

 

thanks

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rourabpaul
Explorer
Explorer
10,664 Views
Registered: ‎08-13-2010

i havd seen lots of threads and post about adc converter in sparttan 3e,many experts giving many solutions,but i have installed all of the codes on boards,but there are no any code that giving successfull results, even i have also a code,where i found my desire results from test bench,but in caes of real time application it was also unsuccessful, is there any external setting are needed for this purpose?

if anyone in this forum have any code about adc which was loded succesfully pls post me

 

Rourab Paul

rourabpaul@gmail.com

 

Tags (1)
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rourabpaul
Explorer
Explorer
10,499 Views
Registered: ‎08-13-2010

pls help me.

is there anyone???

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eteam00
Professor
Professor
10,494 Views
Registered: ‎07-21-2009

To rourabpaul,

 

You might get  some response if you:

  • start a new thread
  • detail which board, which FPGA, which ADC you are using.
  • include specifics of simulation behaviour (more than "doesn't work")
  • include specifics of what DOES work.

These are just suggestions.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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10,388 Views
Registered: ‎02-28-2011

hi

I had downloaded this code and one file is missing.

file name :   vme.vhd

 

thanks and regards

Neeraj

 

neerajsharma341@gmail.com

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Anonymous
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tkdon
Visitor
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Registered: ‎04-05-2011

Hello,

 

So I didn't know wether it was best to start a new thread for this highly related question. I wrote my own driver in VHDL  for the ADC and DAC, where the former is very similar to the one in adc2.rar.

 

Three questions:

- I'm actually a bit puzzled about how to connect the DAC and ADC to the Microblaze, since i´d assume i'd still have to use some sort of FSL/OPB/PLB bus to somehow talk to the device using the ADC and DAC drivers, which use SPI. What to do here?

 

- Also, does anyone have a simple sample code in C to communicate with the ADC (i.e. read data into a variable etc.) ?

 

I notice that the timing requirements of the DAC allows me to run the SPI bus at 50 MHz, while the ADC does not. Is the reason for the counters in adc2.vhd in adc2.rar to establish some sort of delay?

My design originally used a clock divider instead though... but i have modified it to the same as adc2.vhd.

 

I have searched this forum, and did find something regarding question 2: http://forums.xilinx.com/t5/EDK-and-Platform-Studio/ADC-DAC-Tutorials/td-p/44909 but it seems like they used the already availabe delta-sigma ADC IP core in XPS for this...

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eteam00
Professor
Professor
5,540 Views
Registered: ‎07-21-2009

So I didn't know wether it was best to start a new thread for this highly related question.

  • You should start a new thread.
  • You have posed several new questions.

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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celojan
Visitor
Visitor
5,351 Views
Registered: ‎02-07-2011

Hi, im also trying to comunicate ADC with microblaze.

 

Im using the IPCORE SPI v2.01a for SPI comunication. Im read some papers, i think that the best way to generate the signal of ADV_CONV is an IPCORE GPIO. In the attachment image you can see the general conexion.

 

conexion.jpg
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