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Observer
Observer
10,382 Views
Registered: ‎07-13-2008

Spartan3E DAC Verilog code without microblaze and low pass filter design

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Hi buddy,

 

I am designing a dds system that generate analog waveform finally, so I need DAC and low pass filter.

 

Could you provide some link that has DAC verilog or VHDL without MicroBlaze and Low pass filter code?

 

Or could you give me some sugestions?

 

Thanks so much.

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Teacher
Teacher
12,778 Views
Registered: ‎07-09-2009

Hi

 

I'm a little confused,

 

A dac can not be implimented in an FPGA, as the FPGA has no analog output.

  typicaly you have an exteranl DAC chip, and the filtering is also done in analog.

 

If you have a low frequency, KHz region analog needed, you could make  a PWM output of the FPGA, with a low pass filter, or if only a few bits of resolution are required, then you could use a resistor netrwork on the output of the FPGA.

 

Look at companies like TI, Nat semi, NXP, LTC et all for DAC chips.

 

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Teacher
Teacher
12,779 Views
Registered: ‎07-09-2009

Hi

 

I'm a little confused,

 

A dac can not be implimented in an FPGA, as the FPGA has no analog output.

  typicaly you have an exteranl DAC chip, and the filtering is also done in analog.

 

If you have a low frequency, KHz region analog needed, you could make  a PWM output of the FPGA, with a low pass filter, or if only a few bits of resolution are required, then you could use a resistor netrwork on the output of the FPGA.

 

Look at companies like TI, Nat semi, NXP, LTC et all for DAC chips.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Observer
Observer
10,355 Views
Registered: ‎07-13-2008

Yell, I made mistake.

 

There is DAC chip named LTC2624 in Spartan 3E board.

  

And so the low pass filter should be generated inside FPGA before it is transmitted to DAC chip?

 

I am not sure for this. 

 

Thank you. 

 

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Observer
Observer
10,229 Views
Registered: ‎07-13-2008

One more thing, the chip suppot the SPI mode, and I could not search for the exact verilog code.

 

 Does some one could give me some link about the SPI Verilog code? Just simple implementation.

 

Because I found it two compex in opencores. 

 

Thank you. 

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Teacher
Teacher
10,217 Views
Registered: ‎07-09-2009

Hi

 

can't help with verilog I'm afraid.

 

SPI is 'just' a simple serial three wire  data / clock / enable  line.

 

Unfortunatly , it's not an actual standard, there is a default sort of understanding, such as the pin names MISO, MOSI etc, but

 

  Such things as

     clock speed

     number of bits of data

     check sums 

     Phase of clock to data

     Polarity of the enable

     can clock be stoped 

     protocole on the line

 

are not defined, 

 

So you either need to use a core type, where everythign can be selected, or role your own.

  ready the data sheet of the dac, see just what you need to do,

 

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Observer
Observer
10,114 Views
Registered: ‎07-13-2008

 

Could you give me a hand on the following issue? 

 

 

I got a sine waveform from direct digital synthesizer(DDS), which is 12MHz, and the DDS frequency is 100MHz, that means the output data is generated every 10ns.

 

I want to send the data to LTC2624, and SPI communication protocol is 24bits.

 

The SPI protocol runs the maximum speed is 50MHz.

 

So for each data generated from DDS is 10ns, while the time to transmit the data is 20ns*24=480ns.

 

Even I use a FIFO between the DDS and DAC SPI module, the waveform is weird.

 

From oscilloscope, the frequency is 12ns.

 

Is it possible to transmit so-fast DDS signal over DAC SPI communication protocol?

 

Thank you so much. 

 

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Teacher
Teacher
10,111 Views
Registered: ‎07-09-2009

Hi

 

easy answer, no.

 

 Quick look at the LTC2624, to me it looks like it's designed for low frequency stuff, with a settling time of around 10 us, your not going to get more than a few 10's of KHz out of it MAX.

 

 

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Observer
Observer
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Registered: ‎07-13-2008

How about I use FIFO between the fast DDS and slow DAC module?

 

do you think it works? 

 

Thank you. 

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Teacher
Teacher
10,095 Views
Registered: ‎07-09-2009

How would a FIFO help ?

 

What is the data rate in to the FIFO ? What is the data rate out ?

 

 

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Observer
Observer
10,090 Views
Registered: ‎07-13-2008

data rate into FIFO is 10ns;

 

data rate out 1000ns;

 

 

Or I don't use FIFO,just direct sample DDS output.

 

 

And I don't get 12MHz output, instead, I get 12MHz/100=  0.12MHz to show the sine waveform.

 

May be FIFO is not useful in this design. 

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Teacher
Teacher
7,825 Views
Registered: ‎07-09-2009

And what frequency sine wave do you want out of the DAC ?

 

BTW: It's bad etiquette to post same question in more than one forum.

 

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Observer
Observer
7,823 Views
Registered: ‎07-13-2008

Sorry for that.

 

I will re-organize them  and put them together.

 

Thank you for reminding.

 

 

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7,766 Views
Registered: ‎12-30-2009

Hello

I am working with LTC1407 A/D on spartan3E,I wrote the program which impleets both amplifier and ADC with SPI protocol.my problem is when I apply analog volatge to ADC(VINA,just using channel 0),LED's light which represent the 8 most significant bits(digital corresponding of analog volatge) changes accordingly,but it is not equivalent to what I calculated with the formula provided on data sheet from Xilinx which is D[13:0]=Gain*(Vin-1.65)*8192/1.25v.can anyone help me what the problem is?please tell me your ideas.
thanks

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Teacher
Teacher
7,762 Views
Registered: ‎07-09-2009

Hi

 

do you want to tell us what you do get ?

 

Thought is can you increase the voltage and see what voltage change you get for each bit change ?

 

You could well have the bits inverted / reversed, offset binary , 2's compliment or what.

 

I'd get in there with chip scope and have look if I was you

 

You also might want to bring this up as a new topic, as this old one might not get looked at by many people.

 

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7,760 Views
Registered: ‎12-30-2009
I changed voltage with step of 0.1 volt ,so more than one bit changes each time (represented in LEDs).I also calsulated the invert and two's compliment to see if they match with what I see on LEDs ,but they didn't . the thing is ,it also understand negative value ,when volatge getting bigger than 1.65( in v=1.7 till v=2.9),bit 12 will be on which is the 7th LED.I just can see bit 6 to bit 13 on LED,and for volateg less than 1.65(v=0.4 till v=1.6) that bit is off.
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Observer
Observer
7,754 Views
Registered: ‎07-13-2008

Hi drjohnsmith

 

Thans for reminding.

 

In this project, the LTC2624 can only support low frequency, and the solution is convert the serial data to parallel.

 

So, in the Spartan3E FPGA board, we will use a parallel board to connect the extended port and use a high frequency ADC chip.

 

We will continue after school begins.

 

Thank you for your concern.

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Observer
Observer
7,753 Views
Registered: ‎07-13-2008

Sorry, I aslo have no idea of this problem.

 

Hope someone can give you some idea.

 

And may be you can start a new topic regarding to your problem so that people will see that.

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Observer
Observer
7,131 Views
Registered: ‎03-18-2010

I recently purchased a spartan3a starter kit and was planning, among other things, to use it as a dds function generator.

I am dismayed to see how slow the dac [and adc] are. The board has a 133 MHz clock and a dds that should be able to put out >30 MHz, and yet the dca is pedestrian. Trying to save power or cost? I did preliminary check and couldn't find a higher speed replacement part that would fit. I guess I will buy a dds board to do that job.

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