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gteague
Contributor
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Registered: ‎03-16-2012

Targeted reference design ZCU102 missing contraints

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Hello

 

I am trying to follow the steps for

Zynq UltraScale MPSoC Base TRD 2017.2 - Design Module 6

 

http://www.wiki.xilinx.com/Zynq+UltraScale+MPSoC+Base+TRD+2017.2+-+Design+Module+6

 

When I open the project in Vivado to build the PL portion, the following constraints files are missing:

timing.xdc

pin_zcu102.xdc

misc.xdc

 

I am using the following version:

rdf0429-zcu102-es2-base-trd-2017-2.zip

 

Does anyone know where I will be able to find these files? I searched through the extracted ZIP file.

 

Thanks

 

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kvasantr
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Registered: ‎04-12-2017

Hello @gteague

 

Yes, In previous versions of ZIP files it was missing xdc files.

 

Please download latest versions of TRD from below link:

https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html#documentation

 

Please go for rev 2 files.

Make sure you are using the Vivado version that is bundled with 2017.2 SDx, not stock 2017.2 Vivado as that will not work.

 

Hope this helps. 

Thank you.

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samk
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Registered: ‎10-04-2017

Hi @gteague,

 

The files are located under:

rdf0429-zcu102-es2-base-trd-2017-2-rev2.zip\rdf0429-zcu102-es2-base-trd-2017-2\pl\zcu102_es2_base_trd\zcu102_es2_base_trd.srcs\constrs_1\imports\constrs

 

I downloaded the zip file from the documents page for the ZCU102.

 

Regards,

Sam

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kvasantr
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Registered: ‎04-12-2017

Hello @gteague

 

Yes, In previous versions of ZIP files it was missing xdc files.

 

Please download latest versions of TRD from below link:

https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html#documentation

 

Please go for rev 2 files.

Make sure you are using the Vivado version that is bundled with 2017.2 SDx, not stock 2017.2 Vivado as that will not work.

 

Hope this helps. 

Thank you.

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