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Visitor reigngt09
Visitor
11,008 Views
Registered: ‎09-02-2015

To rebuild the project, under impl/build, enter "make"

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Hi  I bought the Xilinx Video Broadcast kit which has the ML605 and HD SDI daughter board. I implemented the other source files for xapp 1075 and I managed to compile and generate a bitstream. 

 

However I am trying to build xapp 591 and it doesnt give me similar instructions like xapp 1075. It just says the following:

5. INSTALLATION AND OPERATING INSTRUCTIONS

1) Install the Xilinx ISE 14.1 or later tools.
2) To rebuild the project, under impl/build, enter "make"

6. SUPPORT

To obtain technical support for this reference design, go to
www.xilinx.com/support to locate answers to known issues in the Xilinx
Answers Database or to create a WebCase.

 

How do i enter make and where do i enter it? Do i implement it in tcl or cmd, how do I change the directory to execute that make file. Will it open up in ISE? The instructions are not very clear and assumes that everybody know what's going on. Please can you help me build this project.

 

Thanks

 

Ritesh

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Visitor reigngt09
Visitor
20,768 Views
Registered: ‎09-02-2015

Re: To rebuild the project, under impl/build, enter "make"

Jump to solution

I managed to build the project, the manual way by making ml605_quad_sdi_passthu.v my top level file and then copy all the missing HDL files and IP cores into Xilinx ISE. It works fines now. 

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Community Manager
Community Manager
10,742 Views
Registered: ‎07-23-2015

Re: To rebuild the project, under impl/build, enter "make"

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@reigngt09 Which version of ISE you using for these XAPP's? 

- Giri
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Visitor reigngt09
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10,739 Views
Registered: ‎09-02-2015

Re: To rebuild the project, under impl/build, enter "make"

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I am using version 14.7 ISE

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Visitor reigngt09
Visitor
20,769 Views
Registered: ‎09-02-2015

Re: To rebuild the project, under impl/build, enter "make"

Jump to solution

I managed to build the project, the manual way by making ml605_quad_sdi_passthu.v my top level file and then copy all the missing HDL files and IP cores into Xilinx ISE. It works fines now. 

0 Kudos