05-29-2013 11:32 AM
I am trying to build the CDMA Benchmark demo app described in UG669 for the SP605 demo board.
I have followed all the steps in UG669 to add the AXI_CDMA and PERF_AXI (UG669 pages 30-34), but when I try to generate the bitstream in ISE 13.2, I get 3 timing errors and the build fails.
Has anyone successfully build this demo and ran it on an SP605 board?
05-29-2013 11:56 AM
I don't find ug669 anywhere. Perhaps it was removed due to problems? Contact who you bought your board from.
10-21-2013 09:57 AM
I have some trouble similar you have, I am working with that card, same demo (UG669 for SP605) but when I try to synthesize I can't pass from this warning:
"EDK:4059 - INSTANCE: Soft_Ethernet_MAC, Overriding connection of PORT:
AXI_STR_RXS_ARESETN, VALUE: AXI_STR_RXS_ARESETN - which is part of the
connected BUSIF: S_AXI -
stem\system.mhs line 592"
I have synthesized it a lot of times about 3 hours but the result is the same. Do you have an idea? Could you fix your trouble? Could you find a better tutorial?. My trouble is that I'm trying to learn AXI protocol but I can't find an efective tutorial about it.
Any help is welcome.
10-26-2013 01:50 AM
Which version of tools are you using?
10-29-2013 03:54 PM
Well, I'm working with Xilinx ISE 14.4 but in fact I could fix the previous trouble, It just needed more time to synthesize but I had to wait for 5 hours long. But now I have a new trouble, I need a CDMA tutorial for SP605 demo card. I was looking for someone but all of them are made for Zynq card and steps are different, does anyone have more information about it?
11-02-2013 02:36 AM
I think you are following http://www.xilinx.com/support/documentation/boards_and_kits/ug669_ml605_sp605_hw_tutorial_axi.pdf
FYI: The BRD (Base reference designs) provided by Xilinx is ISE tool version sensitive. That means the ISE tool version should match with BRD make version. For example if BRD made for ISE 13.X versions does not guaranteed for ISE 14.X tools.