Unable to program IDT5V9885 on a ML509 board

[dadolfss]

Hi,
 
I have a ml509 board where I have problems programming the IDT5V9885 through the J3 JTAG interface. After failing to program the clocks as desired I have also tried to restore factory settings with the ML50X_clock_setup.svf file supplied on the Xilinx web page.
 
This fails with the following message:
-----------
ScanDR 32 TDI(00000000) TDO(003AC067) Mask() Smask()
ERROR:iMPACT - Failed ScanDR: TDO does not match Expected TDO
ERROR:iMPACT - TDO ReadBack : ffffffff
ERROR:iMPACT - TDO Expected : 003ac067
----------
 
At this point I have used a jtag analyzer and it seems to be sending the correct data through the interface but TDO remains high at all times. Using an oscilloscope none of the output clocks of the IDT5V9885 are oscillating neither the X2 xtal directly connected to the IDT5V9885. This leads me to believe that during my attempts to program the custom clocks the XDRV in the IDT5V9885 register has been written with "11" making it expect an external clock instead of driving the xtal.
 
"XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTAL_IN with external clock-default);" from  ftp://ftp.efo.ru/pub/idt/5V9885_datasheet.pdf
 
Since it seems I cannot reprogram the IDT5V9885 through the JTAG interface is there any other way of resetting it to factory default settings?
 
-Dan

[eteam00]

Have you verified that the I2C/JTAG pin is pulled to GND when attempting re-programming via JTAG?

-- Bob Elkind

[dadolfss]

J14 is grounding the pin so JTAG programming is active. I have tried lower clock speeds for JTAG programming just in case the cable connection would be of lower quality . I have also measured all pins directly on the IDT5V9885 and all supply voltages and gnd pins are as expected. I also measured to confirm the J3 JTAG connection with the pins on the IDT5V9885 itself.

Pins 4&5 connected to the xtal are both 0V as expected if XDRV register is written with “11” (external clock expected instead of connected xtal). Pin3/TP1 is high indicating clock loss since no external clock is connected.

What I don’t understand is that TDO is constantly high during execution of the clock programming file. Even with no external clock connected to pin 4 or a broken xtal I would still expect data being driven out of TDO with the help of TCK.

Any Ideas?

[hirschdaumen]

---

@dadolfss wrote:

Even with no external clock connected to pin 4 or a broken xtal I would still expect data being driven out of TDO with the help of TCK. 

---

I vaguely remember that I have to program the IDT5V9885 first before i can do a boundary scan test on an own board. If it is blank, there's no output on TDO. What Xilinx did is to add an IDCODE check just at the beginning of thier "ML50X_clock_setup.svf" file that fails when there is no TDO output. Try to remove the lines

//
SIR 4 TDI (2);
SDR 32 TDI (00000000) TDO (003AC067);

from "ML50X_clock_setup.svf" to just dump the configuration data into the IDT5V9885, without further checks, powercycle the board and check the clock outputs again.

[dadolfss]

I have tried exactly this with the slowest JTAG setting I could set in iMPACT to make sure the cable connection would not impact the result. There is no change in the outputs of the IDT5V9885 (TDO also still constantly high).

In the block diagram of the IDT5V9885 on page two in the datasheet linked in the first post the Xtal/external ref clock is going into the control block programmed by the JTAG so I wonder if further programming is even possible without these?

[hirschdaumen]

I never used the IDT5V9885 with a crystal, but with an oscillator on CLKIN.

It would not consider it as a good design if JTAG doesn't work without external clock. But not giving a TDO output when the device is not programmed isn't a good design, either.

[eteam00 · Accepted solution]

Don't overlook the availability of apps support from IDT.

-- Bob Elkind