Hi, I am going to use the RXRECCLKOUT from the GTY Transceiver as a clock of a logic block. However, I found that if I directly use it in the design. there is an error during synthesis: [Vivado 12-1411] Cannot set LOC property of ports, Site location (GTYE3_COMMON_X0Y2) is not valid for the shape with the following elements: rxrecclkout_chx0y8_p_OBUF_inst rxrecclkout_chx0y8_p
After reading PG182, I added the OBUFDS_GTE3 and then use the output (rxrecclkout_chx0y8_p) as the logic clock source.
But if I use the rxrecclkout_out as clcok source instead of rxrecclkout_chx0y8_p. There is no error during synthesis but during bitstream generation: [DRC RTSTAT-2] Partially routed nets: 1 net(s) are partially routed. The problem bus(es) and/or net(s) are usb_phy_gty_inst/inst/gen_gtwizard_gtye3_top.usb_phy_gty_gtwizard_gtye3_inst/gen_gtwizard_gtye3.gen_channel_container.gen_enabled_channel.gtye3_channel_wrapper_inst/channel_inst/rxrecclkout_out.
Finally, I can only obtain an error free bitstream file by mapping the rxrecclkout_chx0y8_p and rxrecclkout_chx0y8_p as output and then input it through another differetial I/O externally.
So, I would like to ask is there any method such that I can use RXRECCLKOUT from the GTY Transceiver directly inside my code?