UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
179 Views
Registered: ‎11-20-2018

Using si5324 in zc706.

Hi. i have question about si5324. Now i', using zc706.

 

In UG954( zc706 user guide),  si5324 out clk is used for MGTREFCLK1 in Quad 110.

-----------------------------------------------------------------------------

• Quad 110:
° MGTREFCLK0 - FMC_HPC_GBTCLK1_M2C clock
° MGTREFCLK1 - SI5324_OUT_C_P/N jitter attenuator clock
° Contains 4 GTX transceivers allocated to FMC_HPC_DP[7:4]_C2M_P/N

------------------------------------------------------------------------------

SI5324 is jitter attenuator, so there are input clk pin/ output clk pin like below.

20190718_102829.png

 

REC_CLOCK_C P/N are input clk pins for si5324. 

And REC_CLOCK P/N are connected into AD20,AE20 pin on FPGA XC7Z045.

My questions are

1. If i want to use 200Mhz for GT_REF_CLK,  i have to make 200Mhz by using clocking wizard, and then output this clock to AD20,AE20.

   Am I right?

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
135 Views
Registered: ‎06-21-2018

Re: Using si5324 in zc706.

0 Kudos