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brian.trotter
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Registered: ‎11-09-2012

VC707 AXI Ethernet Subsystem Vivado Warning "Cannot set LOC property of ports" for GT refclk

The following occurs with both my own design and the Xilinx BIST reference design for the VC707, in 2015.4 and 2016.4 (and other) versions of Vivado. With the AXI 1G/2.5G Ethernet Subsystem configured in IP Integrator with Board based IO Constraints and DIFFCLK set to "sgmii mgt clk", and Vivado configured for OOC synthesis, the following critical warnings are reported in synthesis:

 

[Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance U0/core_clocking_i/ibufds_gtrefclk on site AH8. The location site type does not match the instance type. ["[path omitted]/bd_0/ip/ip_2/bd_5739_pcs_pma_0_board.xdc":4]
[Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance U0/core_clocking_i/ibufds_gtrefclk on site AH8. The location site type does not match the instance type. ["[path omitted]/bd_0/ip/ip_2/bd_5739_pcs_pma_0_board.xdc":5]

Where the offending lines of the XDC file are:

set_property BOARD_PIN {sgmii_mgt_clkp} [get_ports gtrefclk_p]
set_property BOARD_PIN {sgmii_mgt_clkn} [get_ports gtrefclk_n]

The clock pair ends up getting placed correctly and the design works, so I have been ignoring the warnings. What is the cause of the warnings? Is this a bug in the IP core or Vivado, or should I be doing something differently to prevent the warning?

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venkata
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Registered: ‎02-16-2010

can you check the device part number of your project? the warning seems to refer to targeting a clock to a non-clock capable IOs.
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brian.trotter
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Registered: ‎11-09-2012

@venkata, my project is based on the built-in VC707 board device in Vivado [Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)]. As I said, these same warnings are issued with the Xilinx BIST project for this board, which can be found here. If you build that project, I believe you will find the same warnings. That is a Xilinx design, also based on the built-in VC707 board device. Please take a look at that design.

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brian.trotter
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Registered: ‎11-09-2012

Can someone from Xilinx please look into this?

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brian.trotter
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Registered: ‎11-09-2012

@venkata, Xilinx, anyone?
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brian.trotter
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Registered: ‎11-09-2012

Can someone from Xilinx please take a look at this and respond?
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eengin
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Registered: ‎03-16-2014

I do see the same problem. Usign an Ethernet Subsytem in VC707, Vivado 2016.4 I get the same critical warning. And I also wonder if that is a bug (as the design works OK for now) or something that really needs to be taken care of? Not so hard to replicate. Just use an Ethernet Subsytem in your block design and it should appear.

 

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